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PM73487 qrt pmc-sierra, inc. long form data sheet pmc-980618 issue 3 622 mbps atm traffic management device released datasheet PM73487 qrt 622 mbps atm traffic management device datasheet released issue 3: jun 1999
copyright ? 1998 pmc-sierra, inc. all rights reserved PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet aal1gator, aal1gator2, evil twin switching, qrt, qse, and saturn are trademarks of pmc-sierra, inc. amcc is a registered trademark of applied microcircuits corporation. i960 is a registered trademark of intel corporation. national semiconductor is a registered trademark of national semiconductor corporation. is a trademark of pmc-sierra, inc. vitesse is a trademark of vitesse semiconductor corporation. all other brand or product names are trademarks of their respective companies or organizations. u.s. patents 5,557,607, 5,570,348, and 5,583,861
? 1999 pmc-sierra, inc. 105-8555 baxter place burnaby bc canada v5a 4v7 phone: 604.415.6000 fax: 604.415.6200 in any event, no part of this document may be reproduced in any form without the express written consent of pmc-sierra, inc. pmc-sierra, inc. PM73487 qrt pmc-980618 issue 3 622 mbps atm traffic management device released datasheet public revision history issue number issue date details of change issue 1 march 1998 creation of document issue 2 october 1998 this data sheet includes: registers added in b version of device: rx_queue_engine_test - bits 26:16 tx_queue_engine_test - bits 22:15 queue_engine_condition_pres_bit s queue_engine_condition_latch_b its queue_engine_int_mask rx_lower16_scg_config rx_lower16_scg_state rx_lower32_scg_config rx_lower32_scg_state rx_lower48_scg_config rx_lower48_scg_state tx_lower4_scg_config tx_lower4_scg_state tx_lower8_scg_config tx_lower8_scg_state tx_lower12_scg_config tx_lower12_scg_state updated rx_service_table issue 3 june 1999 production release version
PM73487 qrt pmc-sierra, inc. long form data sheet pmc-980618 issue 3 622 mbps atm traffic management device released datasheet
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet viii table of contents 1 system applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 qrt system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 622 mbps switch configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 32 x 32 switch application (5 gbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 64 x 64 switch application (10 gbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.5 5 gbps to 20 gbps application example - seamless growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.6 5 gbps to 160 gbps application example C lan-to-wan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 theory of operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 interface descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.1 switch fabric interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.2 phase aligners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.3 utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.4 cell buffer sdram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.5 channel ram (ch_ram) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.6 address lookup ram (al_ram) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.7 ab_ram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.8 host processor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.9 se_soc encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.10 bp_ack encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.11 relation between external cell_start and local cell_start . . . . . . . . . . . . . . . . . . . . . . 17 2.3 cell flow overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 utopia operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.2 utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.5 receiver operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.5.1 receive channel lookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.5.2 receive vc (channel) queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.5.3 receive channel ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.5.4 receive congestion management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.5.5 receive queue service algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.5.6 receive sequencing algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.6 transmitter operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6.1 transmit queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6.2 transmit congestion management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6.3 transmit queue service algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.6.4 transmit resequencing algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.6.5 transmit recovery algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.6.6 transmit multicast cell background process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.6.7 transmit multicast congestion management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.7 system diagram of internal qrt blocks and external ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3 fault tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet ix 3.1 the data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.1.1 utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.1.2 switch fabric interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2 fault detection and isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2.1 memory parity checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2.2 utopia interface fault detection and recovery mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2.3 switch fabric fault detection and recovery mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2.4 tables of switch fabric interface failure behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.1 package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2 signal locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.3 signal descriptions (372 signal pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.1 processor interface signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.3.2 statistics interface signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.3.3 switch element interface signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.3.4 ch_ram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.3.5 al_ram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.3.6 abr_ram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.3.7 receive cell buffer drams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.3.8 transmit cell buffer drams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.9 utopia atm layer interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.3.10 boundary scan signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.3.11 miscellaneous signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5 physical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.1 utopia timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.2 dram external memory timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3 sram timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.4 qrt-qse interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.4.1 switch fabric cell formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.5 processor interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.6 miscellaneous timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7 microprocessor ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.1 microprocessor ports summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.2 microprocessor ports bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.2.1 revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.2.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.2.3 test_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.2.4 sram_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.2.5 switch_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.2.6 ram bist result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.2.7 marked_cells_count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.2.8 condition_pres_bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 7.2.9 condition_latch_bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet x 7.2.10 intr_mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 7.2.11 utopia_config. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 7.2.12 ut_priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7.2.13 ut_enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 7.2.14 tx_ut_stat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.2.15 tx_ut_wd_alive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.2.16 rx_cell_start_align (internal structure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.2.17 rx_queue_engine_test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.2.18 tx_queue_engine_test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7. 2. 19 queue engine condition_pres_bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 7. 2. 20 queue_engine_condition_latch_bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7. 2. 21 queue_engine_int_mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 7.2.22 rx_dir_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 7.2.23 rx_dir_state (internal structure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 7.2.24 tx_dir_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 7.2.25 tx_dir_state (internal structure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 7.2.26 rx_sent_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 7.2.27 rx_dropped_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 7.2.28 tx_sent_cells. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 7.2.29 tx_dropped_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7. 2. 30 rx_lower16_scg_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7. 2. 31 rx_lower16_scg_state (internal state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7. 2. 32 rx_lower32_scg_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 7. 2. 33 rx_lower32_scg_state (internal state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 7. 2. 34 rx_lower48_scg_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 7. 2. 35 rx_lower48_scg_state (internal state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 7. 2. 36 tx_lower4_scg_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 7. 2. 37 tx_lower4_scg_state (internal state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 7. 2. 38 tx_lower8_scg_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 7. 2. 39 tx_lower8_scg_state (internal state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 7. 2. 40 tx_lower12_scg_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 7. 2. 41 tx_lower12_scg_state (internal state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 8 internal ram memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 8.1 internal ram summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 8.2 transmit service class ram (tsc_ram) summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 8.2.1 transmit service class queue (tx scq) control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 8.3 receive service class ram (rsc_ram) summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 8.3.1 receive service class (rx sc) control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 8.4 virtual output control ram (vo_ram) summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 8.4.1 transmit vo control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 8.4.2 transmit sc control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 8.4.3 transmit multicast sc control block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 64 8.5 receive switch fabric control ram (rsf_control) summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 8.5.1 rx_rsf_config (internal structure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet xi 8.5.2 rx_rsf_tag (internal structure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 8.5.3 rx_rsf_new_vpi_vci (internal structure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 8.5.4 rx_rsf_sn_chan (internal structure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 8.5.5 rx_rsf_er_cell_ptr (internal structure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 8.6 transmit switch fabric control ram (tsf_control_ram) summary . . . . . . . . . . . . . . . . . . . . . . 169 8.6.1 tx_tsf_sn_chan (internal structure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 8.7 test access to the receive utopia ram (ru_ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 0 8.8 test access to the transmit utopia ram (tu_ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1 8.9 test access to receive switch element ram (rs_ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2 8.10 test access to transmit swith element ram (ts_ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 9 external ram memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 9.1 external ram summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 9.2 address lookup ram (al_ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 9.2.1 vi_vpi_table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 9.2.2 vci_table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 9.2.3 multicast cell instance control block (internal structure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 77 9.2.4 rx_next_cell (internal structure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 9.2.5 transmit cell buffer control block (internal structure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 80 9.2.6 service order control block (internal structure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 9.3 channel ram (ch_ram). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 9.3.1 channel control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 9.3.2 multicast control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 9.4 abr_ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 9.4.1 receive channel queue block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 9.4.2 receive channel statistics block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 9.5 sdram/sgram interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 9.5.1 rx_dram_register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 9.5.2 tx_dram_register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 9.5.3 receive cell buffer sdram/sgram summary (internal structure) . . . . . . . . . . . . . . . . . . . . . . 202 9.5.4 transmit cell buffer sdram/sgram summary (internal structure) . . . . . . . . . . . . . . . . . . . . . 203 10 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 11.1 connecting qrts to qses using gigabit ethernet transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 11.2 connecting to standard serializer/deserializer chipsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 11.3 connecting the qrt to the s/uni-atlas pm7324. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 11.4 relationships among various clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 11.4.1 relationship among the sysclk, se_clk, and the switch speed-up factor . . . . . . . . . . . . . 230 11.4.2 the phase aligner se_clk frequency constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 11.4.3 the sysclk dram refresh constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 11.4.4 relationship between atm_clk and sysclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 11.4.5 relationship between the pclk and the sysclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet xii list of figures figure 1. qrt system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. qrt system overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. 622 mbps switch configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 4. 32 x 32 switch application (5 gbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 5. 64 x 64 switch application (10 gbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 6. 5 gbps atm switch using 16 dual s/unis, 8 qrts, and 1 qse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 7. 10 gbps atm switch using 32 dual s/unis, 16 qrts, and 2 qses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 8. 20 gbps atm switch using 64 dual s/unis, 32 qrts, and 4 qses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 9. 5 gbps to 160 gbps switches modeled using only two cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 10. 5 gbps atm switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 11. 10 gbps atm switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 12. 15 gbps atm switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 13. 20 gbps atm switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 14. qrt system overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 15. se_soc encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 16. bp_ack encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 17. qrt cell-level timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 18. qrt data flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 19. receive utopia operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 20. transmit utopia operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 21. receive standard single cell available polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 22. transmit standard single cell available polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 23. receive utopia multiplexed status polling (msp), including cell transfer. . . . . . . . . . . . . . . . . . . . 22 figure 24. transmit utopia 50 mhz multiplexed status polling (msp), including cell transfer. . . . . . . . . . . . 22 figure 25. vcc channel lookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 26. vpc channel lookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 27. channel linked list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 28. channel linked list C a new cell arrives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 29. channel linked list C a cell is sent to the fabric. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 30. receive channel ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 31. receive channel ring after channel_a becomes run-limited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 32. receive channel ring after channel_b is served but it is not run-limited. . . . . . . . . . . . . . . . . . . . . 29 figure 33. receive channel ring after channel_a gets cell through fabric and is added to ring. . . . . . . . . . . 29 figure 34. receive congestion limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 35. epd/ptd operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 36. epd/ptd with clp operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 37. efci operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 38. steps to send a cell to the fabric. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 39. receive service class (sc) map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 40. transmit per-scq linked list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 41. transmit maximum and congested threshold checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 42. transmit service class (sc) map (per vo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet xiii figure 43. cell playout steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 44. transmit resequencing operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 45. multicast background process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 46. multicast pointer fifo operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 47. system diagram of internal qrt blocks and external ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 48. basic data path through the switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 49. 503-pin epbga top and side views (part 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 49. 503-pin epbga bottom view (part 2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 50. receive utopia 50 mhz timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 51. transmit utopia 50 mhz timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 52. receive dram external memory 100 mhz read timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 53. receive dram external memory 100 mhz write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 54. transmit dram external memory 100 mhz read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 55. transmit dram external memory 100 mhz write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 56. address lookup ram read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 57. address lookup ram write timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 58. channel ram read timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 59. channel ram write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 60. ab ram read timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 61. ab ram write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 62. qrt bit-level timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 63. microprocessor read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 65. reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 66. jtag timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 67. transmit service class ram (tsc_ram) memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 51 figure 68. receive service class ram (rsc_ram) memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 55 figure 69. virtual output control ram (vo_ram) memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 70. boundary scan architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 figure 71. tap controller finite state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 72. connecting the qrt to gigabit ethernet transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 figure 73. connecting the qrt to the rcmp-800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet xiv list of tables table 1. backpressure and acknowledgment encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 2. failure conditions, irt-to-switch fabric interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 3. failure conditions, qse receive interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 4. failure conditions, qse transmit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 5. failure conditions, switch fabric-to-ort interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 6. faults and effects on the network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 7. signal locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 8. processor interface signals (38 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 9. statistics interface signal (1 pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 10. switch element interface signals (47 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 11. ch_ ram interface signals (58 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 12. address lookup ram interface signals (42 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 13. abr_ram interface signals (22 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 14. receive cell buffer ram interface signals (49 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 15. transmit cell buffers ram interface signals (48 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 16. transmit utopia atm layer interface signals (29 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 17. receive utopia atm layer interface signals (27 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 18. test signals (8 signal pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 19. miscellaneous signals (3 signal pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 20. estimated package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 21. qrt-qse interface cell format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 22. qrt-qse interface idle cell format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 23. microprocessor ports summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 24. various ways to configure utopia interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 25. internal ram summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 26. transmit service class queue (tx scq) control block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 27. receive service class (rx sc) control block summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 28. transmit vo control block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 29. transmit sc control block summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 30. transmit multicast sc control block summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 31. receive switch fabric control ram (rsf_control) summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 32. receive utopia cell buffers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 33. transmit utopia cell buffers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 34. address lookup ram (al_ram) summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 35. determining the num_vpi value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 36. vi_vpi_table entry if vpc_entry = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 37. vi_vpi_table entry if vpc_entry = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 38. service order control block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 39. channel ram (ch_ram) summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 40. channel control block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 41. multicast control block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 42. ab_ram summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet xv table 43. receive channel queue block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 44. receive channel queue block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 45. receive cell buffers sdram/sgram summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 46. transmit cell buffers sdram/sgram summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 47. boundary scan pin order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 table 48. prefixes and associated functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 table 49. qrt ram selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 table 50. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 1 product overview the PM73487 622 mbps atm traffic management device (qrt ? ) is an advanced communica- tions device capable of supporting very large, high-performance atm switching systems. the rich feature set of the qrt enables systems to offer many sophisticated network services. the qrt provides 622 mbps utopia (level 1 or level 2) access to switch fabrics composed of pm73488 5 gbps atm switch fabric elements (qses). together, these devices can be used to build architectures with capacities from 622 mbps to 160 gbps. the qrt can also act as a stand- alone 622 mbps switch. the qrt/qse architecture virtually eliminates head-of-line blocking by means of the qrts per- virtual channel (vc) receive queues and congestion feedback from the qse ? switch fabric. the distributed architecture acts as an output-buffered switch by incorporating evil twin switching ? (a congestion-reducing routing algorithm in the switch fabric) and a speed-up factor in the switch fabric (running the fabric faster than the line rate). the qrt uses per-vc receive queues, 64 receive service classes (scs), and 16 transmit scs per each of the 31 virtual outputs (vos) to enable flexible multi-priority scheduling algorithms. the scheduler can be used to ensure quality-of-service (qos) guarantees for constant bit rate (cbr), variable bit rate (vbr), and unspecified bit rate (ubr) vcs. the qrt also provides five separate congestion thresholds, each with hysteresis, that selectively control aal5 early packet discard (epd) and/or cell loss priority (clp)-based cell dropping for ubr support. additional highlights of the qrt include full virtual path indicator (vpi)/virtual channel indi- cator (vci) header translation, separate input and output cell buffers (up to 64k each), virtual path (vp)/vc switching, and support for up to 16k vcs on both the receive and transmit sides. pmc-sierra also offers the qrt device control package, which is a software package that har- nesses the qrts rich feature set and shortens system development times. features queuing algorithms receive ? maintains 64 weighted, bandwidth-controlled scs with per-vc queues. ? provides round-robin servicing of queues within each sc. ? provides per-channel (vp or vc), per-sc, and per-direction congested and maximum queue depth limits. ? provides up to 64k cell buffers. transmit ? provides 31 vos. ? maintains 16 scs for each vo with per-vc accounting.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 2 ? provides per-channel (vp or vc), per-sc queue (scq), per-sc, per-vo, and per- direction congested and maximum queue depth limits. ? provides up to 64k cell buffers. congestion management algorithms ? supports epd and partial packet discard (ppd) for ubr traffic, and as a backup for abr traffic. ? supports clp-based cell discard and explicit forward congestion indicator (efci) cell marking. ? supports three congestion limits (as well as epd, clp, and efci, and/or backpressure) for logical multicast on the transmit side. switching ? supports vc and vp switching. ? supports up to 16k vcs. address mapping ? supports all 12 vp and 16 vc bits through use of a double, indirect lookup table. ? performs header translation at both the input (receive) and output (transmit) directions. input header translation is used to pass the output queue channel number through the switch. multicast ? supports logical multicast with a superior queue-clearing algorithm. diagnostic/robustness features ? checks the header parity. ? counts tagged cells. ? runs error checks continually on all fabric lines. ? checks liveness of control signal lines at both switch fabric and utopia interfaces, working around partial fabric failures. ? checks static random access memory (sram) and dynamic random access memory (dram) parity. statistics features ? in the receive direction, counts cells transmitted and dropped. ? in the transmit direction, counts cells transmitted and dropped on a per-vc basis. i/o features ? provides four switch element interfaces with phase aligners. the phase aligners allow for external serialization of the data stream enabling systems to be built that support device separation of up to 10 meters. ? provides a utopia level 2 multi-phy (mphy) 16-bit, 50 mhz interface. ? provides a 2-level priority servicing algorithm for high and low bandwidth utopia phy layer devices. ? provides a multiplexed address/data cpu interface.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 3 ? provides two 100 mhz, 32-bit, synchronous dram cell buffer interfaces. ? provides three 100 mhz, synchronous sram control interfaces. ? provides a jtag boundary scan interface. compatibility features ? compatible with the atm forum 3.0, 3.1, and 4.0 specifications. ? compatible with the atm forum utopia level 1 and level 2 specifications. ? compatible with the pm73488 atm qse. physical characteristics ? 3.3 v supply voltage. ? 5 v tolerant inputs on the microprocessor and utopia interfaces. ? available in a 503-pin enhanced plastic ball grid array (epbga) package. block diagram figure 1 shows a qrt system block diagram. figure 1. qrt system block diagram receive utopia transmit utopia to switch fabric from switch fabric host interface receive cell sdram control ssram 622 mbps atm traffic mgt device (qrt) PM73487 transmit cell sdram
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 4 1 system applications the qrt, together with the qse, support a wide range of high-performance atm switching sys- tems. these systems range in size from 622 mbps to 160 gbps. the systems can be developed such that this scalability is provided with linear cost. another key feature of the qrt/qse archi- tecture is that it is exceptionally fault-tolerant, both in the switch fabric and the utopia inter- face. this section contains a quick overview of the qrt and several example applications: ? a stand-alone 622 mbps switch using a single qrt, ? a 5 gbps switch using qrts and a qse, ? a 10 gbps switch using qrts and qses, ? a switch architecture using qrts and qses that scales from 5 gbps to 20 gbps, ? a switch architecture using qrts and qses that scales from 5gbps to 160 gbps 1.1 qrt system overview the qrt provides 622 mbps of input and output buffered access to switch fabrics composed of qses (32 x 32 pm73488s). in addition, the qrt supports a stand-alone, purely output-buffered 622 mbps switch mode. head-of-line blocking, commonly associated with input buffers, is virtu- ally eliminated via per-vc receive queues, three types of per-cell switch fabric feedback, and per- vc cell selection algorithms. the qrt also provides eight separate congestion thresholds, each with hysteresis, that selectively control aal5 early packet discard (epd)/packet tail discard (ptd), clp-based cell dropping, and/or efci marking. eight separate maximum thresholds are also supported. additional highlights of the qrt include full vpi/vci header translation, sepa- rate input and output cell buffers (up to 64k each), virtual path connection (vpc)/virtual chan- nel connection (vcc) connections, and up to 16k vcs. the qrt provides a bidirectional connection between a utopia level 2 interface and 4-nibble wide, 66 mhz switch fabric inter- faces, as shown in figure 2 on page 5 . a significant switch speed-up factor, up to 1.6 times the line rate, is used to support full throughput for many switch fabric configurations.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 5 1.2 622 mbps switch configuration the qrt can be used in a stand-alone application that supports atm switching up to 622 mbps, as shown in figure 3. the four switch fabric interfaces are looped back to the qrt, allowing the utopia interface to be fully used. in this application, the qrt operates as an output buffered switch.. figure 2. qrt system overview figure 3. 622 mbps switch configuration physical and/or atm layers qrt (PM73487) qse (pm73488) input cell sdram output cell sdram multicast sram receive receive nibble data transmit nibble data transmit feedback receive utopia level 2 interface transmit utopia level 2 interface control ssram cells are stored in per- priority queues on the output with per-vc accounting cells are stored in per-vc queues on the input and respond to per-cell aal1 sar processor (pm73121) s/uni-quad (pm5349) qrt (PM73487) 2m 2m 155m 155m utopia level 2 multi-phy interface 1 1 8 4 ? ? ?
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 6 1.3 32 x 32 switch application (5 gbps) figure 4 shows a basic 32 32 switch application (5 gbps) using eight qrts and one qse. 1.4 64 x 64 switch application (10 gbps) figure 5 shows a 64 64 switch application (10 gbps) using 16 qrts and 6 qses. this applica- tion uses qses in a 3-stage fabric. this sized system can be implemented in a single 19-inch rack. figure 4. 32 x 32 switch application (5 gbps) figure 5. 64 x 64 switch application (10 gbps) qrt #1 (PM73487) receive input qrt #8 (PM73487) receive input qse (pm73488) 4 4 622 mbps aggregate 622 mbps aggregate receive utopia level 2 qrt #1 (PM73487) transmit output qrt #8 (PM73487) transmit output 4 4 622 mbps aggregate 622 mbps aggregate transmit utopia level 2 qrt #1 (PM73487) receive input qrt #8 (PM73487) receive input qse (pm73488) 4 622 mbps aggregate receive utopia level 2 qrt #1 (PM73487) transmit output qrt #8 (PM73487) transmit output 4 622 mbps aggregate qrt #9 (PM73487) receive input qrt #16 (PM73487) receive input 4 qrt #9 (PM73487) transmit output qrt #16 (PM73487) transmit output transmit utopia level 2 qse (pm73488) qse (pm73488) qse (pm73488) qse (pm73488) qse (pm73488) 622 mbps aggregate 622 mbps aggregate receive utopia level 2 622 mbps aggregate 16 16 16 16 4 transmit utopia level 2 622 mbps aggregate 622 mbps aggregate 622 mbps aggregate
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 7 1.5 5 gbps to 20 gbps application example - seamless growth this section illustrates the modularity of the qrt (PM73487) and qse (pm73488) architecture. a 5 gbps system can immediately be created (as shown in figure 6 on page 7 ), and then be upgraded to 10 gbps (as shown in figure 7 on page 7 ), or 20 gbps (as shown in figure 8 on page 8 ). since all these systems are based on a single-stage switch fabric, the per-port cost for each sys- tem will remain the same. figure 6. 5 gbps atm switch using 16 dual s/unis, 8 qrts, and 1 qse figure 7. 10 gbps atm switch using 32 dual s/unis, 16 qrts, and 2 qses switch card ? one qse (pm73488) eight 155 mbps interfaces port card ? two qrts (PM73487s) eight 155 mbps interfaces eight 155 mbps interfaces eight 155 mbps interfaces port card ? two qrts (PM73487s) port card ? two qrts (PM73487s) port card ? two qrts (PM73487s) switch card ? one qse (pm73488) ? ? ? eight 155 mbps interfaces port card 1 ? two qrts (PM73487s) eight 155 mbps interfaces port card 8 ? two qrts (PM73487s) switch card ? one qse (pm73488)
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 8 figure 8. 20 gbps atm switch using 64 dual s/unis, 32 qrts, and 4 qses ? ? ? eight 155 mbps interfaces port card 1 ? two qrts (PM73487s) eight 155 mbps interfaces switch card ? one qse (pm73488) switch card ? one qse (pm73488) switch card ? one qse (pm73488) switch card ? one qse (pm73488) port card 16 ? two qrts (PM73487s)
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 9 1.6 5 gbps to 160 gbps application example C lan-to-wan a powerful application of the qrt and the qse devices is the creation of modules that can be used in a range of switches with only the interconnection changing between different sizes. atm switches from 5 gbps to 160 gbps can be realized with only two unique cards. a port card has one qrt, and a switch card has two qses. the switch fabric consists of three stages, each with 32 qses (or 16 switch cards). to plan for future scalability, the middle stage must be built-in upfront. this is a one-time cost. then, in order to scale in 5 gbps increments, one switch card and its accompanying eight port cards should be added. finer bandwidth scaling is possible by popu- lating the additional switch card with port cards as needed (in increments of 622 mbps). with this switch fabric topology, scaling is possible up to 160 gbps. once the initial middle stage cost has been incurred, the per-port cost for 5 gbps through 160 gbps systems remains almost constant figure 9. 5 gbps to 160 gbps switches modeled using only two cards qrt (PM73487 port card - one qrt one utopia level 2 interface switch card - two qses qse (pm73488 qse (pm73488 x32 x32 x32 x32
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 10 figure 10 shows a 5 gbps atm switch using 8 port cards (8 qrts) and 17 switch cards (34 qses). the middle stage is composed of 16 switch cards. the 5 gbps bandwith is achieved by adding switch card #17 (which is depicted using two boxes: one stage 1 qse and one stage 3 qse), and eight port cards (each of which is depicted using two boxes: one for the rx input side, and one for the tx output side). lines between stage 1 and stage 2, and stage 2 and stage 3 switch cards represent two sets of wires, one to each of the qses in the middle stage switch cards. figure 10. 5 gbps atm switch port card #1 rx input 622 mbps port card #8 rx input 622 mbps switch card #17 stage 1 qse port card #1 tx output 622 mbps port card #8 tx output 622 mbps switch card #17 stage 3 qse switch card #16 switch card #2 switch card #1 x2 x2
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 11 .figure 11 shows a 10 gbps atm switch using 16 port cards (16 qrts) and 18 switch cards (36 qses). here, another switch card and eight port cards have been added to the 5 gbps switch depicted in figure 10. figure 11. 10 gbps atm switch port card #1 rx input 622 mbps port card #8 rx input 622 mbps port card #9 rx input 622 mbps port card #16 rx input 622 mbps switch card #17 stage 1 qse switch card #18 stage 1 qse port card #1 tx output 622 mbps port card #8 tx output 622 mbps port card #9 tx output 622 mbps port card #16 tx output 622 mbps switch card #17 stage 3 qse switch card #18 stage 3 qse switch card #16 switch card #2 switch card #1 x2 x2 x2 x2
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 12 figure 12 shows a 15 gbps atm switch using 24 port cards (24 qrts) and 19 switch cards (38 qses).here, once again, another switch card and eight port cards have been added figure 12. 15 gbps atm switch port card #1 rx input 622 mbps port card #8 rx input 622 mbps port card #9 rx input 622 mbps port card #16 rx input 622 mbps switch card #17 stage 1 qse switch card #18 stage 1 qse port card #1 tx output 622 mbps port card #8 tx output 622 mbps port card #9 tx output 622 mbps port card #16 tx output 622 mbps switch card #17 stage 3 qse switch card #18 stage 3 qse switch card #16 switch card #2 switch card #1 port card #17 rx input 622 mbps switch card #19 stage 1 qse port card #17 tx output 622 mbps port card #24 tx output 622 mbps switch card #19 stage 3 qse x2 x2 x2 x2 x2 x2 port card #24 rx input 622 mbps
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 13 figure 13 shows a 20 gbps atm switch composed of 32 port cards (32 qrts) and 20 switch cards (40 qses). by adding additional sets of a switch card and eight port cards in the same man- ner, this system can scale up to 160 gbps. . . figure 13. 20 gbps atm switch port card #1 rx input 622 mbps port card #8 rx input 622 mbps port card #9 rx input 622 mbps port card #16 rx input 622 mbps switch card #17 stage 1 qse switch card #18 stage 1 qse port card #1 tx output 622 mbps port card #8 tx output 622 mbps port card #9 tx output 622 mbps port card #16 tx output 622 mbps switch card #17 stage 3 qse switch card #18 stage 3 qse switch card #16 switch card #2 switch card #1 port card #17 rx input 622 mbps port card #24 rx input 622 mbps port card #25 rx input 622 mbps port card #32 rx input 622 mbps switch card #19 stage 1 qse switch card #20 stage 1 qse port card #17 tx output 622 mbps port card #24 tx output 622 mbps port card #25 tx output 622 mbps port card #32 tx output 622 mbps switch card #19 stage 3 qse switch card #20 stage 3 qse x2 x2 x2 x2 x2 x2 x2 x2
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 14 2 theory of operations 2.1 overview the qrt is a 622 mbps, full duplex, intelligent routing table which, when used with a switch fab- ric composed of either se or qse devices, can implement atm switches from 622 mbps to 160 gbps. the qrt supports a 16-bit utopia level 2 interface for ease of connection to phy or aal layer devices. four nibble-wide data interfaces connect the qrt to the switch interface. external dram memory devices provide receive and transmit cell buffering, and external sram devices provide control data for the qrt. this section explains the algorithms for the data flow. figure 14 shows an overview of the qrt system. 2.2 interface descriptions 2.2.1 switch fabric interface the qrt switch fabric interface consists of four groups of signals from both the ingress (receive side) and the egress (transmit side). each group consists of a start-of-cell (se_soc_out) sig- nal, a nibble-wide data bus, and a backpressure acknowledgment (bp_ack_in) signal. the start-of-cell (se_soc_out) signal is transmitted at the ingress at the same time as the begin- ning of a cell. se_soc_out on the ingress is common to all four groups. the bp_ack_out signal flows from the egress through the switch fabric, in the direction opposite the data, and indi- cates whether a cell has successfully passed through the switch fabric. other signals associated with the switch fabric interface are the switch element clock (se_clk) and rx_cell_start. to support the highest possible throughput for various switch fabric configurations, a clock speed-up factor of 1.6 is used. that is, the switch fabric is run at a rate that is effectively 1.6 times faster than the line rate. figure 14. qrt system overview qrt (PM73487) receive cell sdram transmit cell sdram control ssram receive utopia level 2 interface transmit utopia level 2 interface to qse host interface from qse
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 15 2.2.2 phase aligners phase aligners are used to allow for extended device separation. the technique used is a clock recovery mechanism that requires only the switch fabric to be frequency synchronous. a master clock is distributed to all devices associated with the switch fabric, and the phase of the clock at each interface is dynamically adjusted to account for skew introduced to the signals. the phase aligner circuitry for each interface responds to the cell start and feedback signals, which contain a high number of transitions to ensure accurate phase adjustment of the clock for data and signal sampling. 2.2.3 utopia interface the qrts utopia interface implements the atm forum standardized 16-bit, level 2 configu- ration, which supports up to 31 virtual outputs (vos) via five address bits. up to 31 phy or aal layer devices with 16-bit utopia level 2 functionality can be connected to this interface, providing full duplex throughputs of 675 mbps. 2.2.4 cell buffer sdram interface the qrt supports two synchronous dram (sdram or sgram) interfaces providing up to 64k of cell buffering in both the receive and transmit directions. each interface consists of a 32- bit data bus, a 9-bit address bus, two chip select signals, and associated control signals. the fre- quency of these interfaces is 100 mhz. both synchronous graphic ram (sgram) and sdram devices are supported. clocking for these two interfaces is provided through the device. 2.2.5 channel ram (ch_ram) interface the qrt supports up to 16k channels through a synchronous sram (ssram) interface. the interface consists of a 32-bit data bus, a 16-bit address bus, and associated control signals. the frequency of this interface is 100 mhz. clocking for this interface is provided through the device. 2.2.6 address lookup ram (al_ram) interface the qrt has data structures in the al_ram, including vpi/vci address translation. the inter- face consists of a 6-bit data bus, a 17-bit address bus, and associated control signals. the fre- quency of this interface is 100 mhz. clocking for this interface is provided through the device. 2.2.7 ab_ram interface the qrt stores the per vc head / tail pointers and sent / dropped counters for the receive direc- tion in the ab_ram. each interface consists of a 17-bit multiplexed address/data bus and associ- ated control signals. the frequency of this interface is 100 mhz. 2.2.8 host processor interface the qrt host processor interface allows connection of a microprocessor through a multiplexed 32-bit address/data bus. the suggested microprocessor for this interface is the intel i960 ? . the microprocessor has direct access to all of the qrt control registers.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 16 2.2.9 se_soc encodings the se_soc and bp_ack signals have guaranteed transitions and special encodings, which are defined in this section and in bp_ack encodings which follows. the se_soc_in and se_soc_out signals have guaranteed transitions and soc encodings as shown in figure 15. the se_soc signals carry a repeating pattern of four zeros and four ones to guarantee transitions required by the phase aligner. the start-of-cell on the data lines associated with an se_soc line is indicated by a change in this pattern. for a valid se_soc, the change in pattern is followed by reset of the background pattern such that it is followed by four zeros and four ones. the first nibble (pres) of the header is coincident with se_soc (change in pattern). 2.2.10 bp_ack encodings figure 16 shows the bp_ack encodings. the bp_ack_in and bp_ack_out signals have guaranteed transitions, and bp and ack encodings. the bp_ack signal is used to signal backpressure/cell acknowledgment to the fabric (qse) at the egress and receive backpressure/cell acknowledgment at the ingress from the fabric (qse). to ensure the transitions required by the phase aligner, the bp_ack signal carries a repeating four zeros, four ones pattern. the actual information is transferred through encoded 7-bit packets that start with a change in this background pattern. the change (an inversion) on the line is fol- lowed by a mode bit, followed by two bits of coded message, and a second inversion (inverse of the first inversion). if it is an acknowledgment packet, this is followed by two bits of code exten- figure 15. se_soc encodings figure 16. bp_ack encodings 4 ones. 4 zeros 4 ones 4 zeros 4 ones 4 zeros. 4 ones 4 zeros. 5 zeros 4 ones 4 zeros. pres. 4 ones 4 zeros 1 one. 5 zeros tsesu tsesu tseho se_clk se_soc_out magnified clk magnified data magnified se_soc_out 4 ones 4 zeros 4 zeros 4 ones inversion1 mode data2 data1 inversion2 data0 code ext 0 clk bp_ack base pattern bp_ack signaling
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 17 sion (these bits are for future use and currently are required to be 00). in the case of a backpres- sure packet, the next bit is the backpressure bit on for low priority multicast cells, followed by one code extension bit. the background is reset to four zeros and four ones after transmission of each packet. the qrt and qse allow back-to-back acknowledgment and backpressure packets. in the case of back-to-back acknowledgment and backpressure packets, the receiving device may see an inverted bit (a 1) followed by the rest of the packet instead of a reset background pattern. one backpressure packet and either one or none acknowledgment packet are expected to be received during a cell time. the receipt of multiple acknowledgment or backpressure packets is a failure condition. table 1 describes the backpressure and acknowledgment encodings. 2.2.11 relation between external cell_start and local cell_start figure 17 shows the relationship between external rx_cell_start and local cell_start signals. table 1. backpressure and acknowledgment encodings mode data 2 data 1 data 0 code ext 0 description 0 1 = backpressure on high priority multicast cell. 1 = backpressure on medium prior- ity multicast cell. 1 = backpressure on low priority multicast cell. 0 backpressure information. this signal is present each cell time, regardless of whether a cell was transmit- ted or not (on that link). this signal is withheld if any problem is detected on the input port. 10000signals no response. treated as acknowl- edgment. 10100signals mid-switch negative acknowl- edgment (mnack). 11000signals output negative acknowledg- ment (onack). 11100signals acknowledgment (ack). figure 17. qrt cell-level timing rx_cell_start high rx_cell_start low cell_start delay cell_start delay clock cycle clock cycle delta delta se_clk external rx_cell_start local cell_start
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 18 delay between the external rx_cell_start and local cell_start is programmable through the rx_cell_start_align register (refer to rx_cell_start_align (inter- nal structure) on page 122 ). the local cell_start impacts the start of cell transmission to the fabric. it also determines the period within a cell time during which the bp_ack_in(3:0) at ingress is valid. as such, the pro- grammable cell_start delay allows the flexibility to synchronize the qrts and qses in a system. 2.3 cell flow overview the qrt functions as a 622 mbps port for an atm switch fabric composed of either the se or qse devices. the qrt transfers cells between a utopia level 2 interface and a switch fabric interface. the device supports header translation and congestion management. the basic flow of cells through the qrt is as follows (see figure 18 on page 19 ): 1. a cell enters the qrt on the receive side from the utopia interface and the channel number is looked up. 2. the cell is then either dropped or transferred to the receive cell buffer dram and queued in the receive queue controller depending on six congestion management checks (both maximum and congested thresholds for the device, service class group (scg), sc, and connection). 3. when an available cell time occurs, four cells are selected by the receive-side scheduler, which reads the cells from the receive cell buffer dram and transmits them from the qrt into the switch fabric. 4. once a cell is received from the switch fabric on the transmit side, it is again either dropped or trans- ferred to the transmit cell buffer dram and queued in the transmit queue controller, depending on ten congestion management checks (both maximum and congested thresholds for the device, vo, sc, ser- vice class group (scg),service class queue (scq), and connection). 5. when the cell is selected for transmission by the transmit-side scheduler, it is removed from the trans- mit cell buffer dram and processed by the transmit multicast/header mapper for corresponding header translation and distribution.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 19 6. the cell then is sent to the utopia interface and exits the qrt on the transmit side. 2.4 utopia operation 2.4.1 general cells received from the utopia interface are first processed by the receive channel lookup block and then queued for transmission within the receive queue controller. the cell waits in the receive cell buffer dram for instruction from the receive queue controller to proceed to the switch fabric interface. 2.4.2 utopia interface the qrt interfaces directly to a utopia interface device without needing an external fifo. the receive side utopia has a 4-cell internal fifo, and the transmit side contains another 4-cell internal fifo. the qrt utopia interface is 16 bits wide and operates at frequencies up to 50 mhz. it provides the following modes: ? utopia level 1 single-phy interface ? utopia level 2 multi-phy interface figure 18. qrt data flow diagram receive utopia cell buffer receive channel lookup ssram controller transmit multicast background transmit utopia cell buffer receive queue controller transmit queue controller receive sdram controller receive switch cell buffer transmit switch cell buffer transmit sdram controller control ssram receive sdram cell buffer transmit sdram cell buffer data to qse feedback from qse feedback to qse data from qse receive utopia level 2 interface transmit utopia level 2 interface
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 20 2.4.2.1 utopia level 2 polling the utopia interface offers three modes of polling, as per the utopia level 2 specification: ? standard single cell available polling ? multiplexed status polling (msp) using four cell available signals ? direct status indication using four cell available signals these polling modes allow the qrt to communicate with many different phy devices. figure 19 shows the qrt polling phy devices in a receive utopia operation. figure 20 shows the qrt polling phy devices in a transmit utopia operation. figure 19. receive utopia operation figure 20. transmit utopia operation qrt (PM73487) to switch fabric data address cell available serial in serial in serial in phy device phy device qrt polls phys to determine if they have cells. phy device qrt (PM73487) data address cell available from switch fabric serial out serial out serial out phy device phy device phy device qrt polls phys to determine if they can accept cells.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 21 2.4.2.1.1 standard single cell available polling in the standard single cell available polling mode, one cell available response occurs every two clocks. figure 21 shows the receive standard single cell available polling. figure 22 shows the transmit standard single cell available polling. figure 21. receive standard single cell available polling figure 22. transmit standard single cell available polling 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930 hh p h pppppppp p ppp pppppp pppp p 01 1f 1f 1f 00 01 1f 1f 02 03 04 05 1f 1f 1f 06 07 1f 00 1 0 10 10 1 10 atm_clk ratm_data(15:0) ratm_add(4:0) /ratm_read_en ratm_clav(3:0) ratm_soc 1 2 3 4 5 6 7 8 9101112131415161718192021222324252627282930 hp p p p pp pp pp p p ppp pppppp ppp 04 1f 1f 1f 00 01 1f 1f 02 03 04 05 1f 1f 1f 06 07 1f 01 0 101 01 1 hh 1f h 01 00 atm_clk tatm_data(15:0) tatm_add(4:0) /tatm_write_en tatm_clav(3:0) tatm_soc tatm_parity
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 22 2.4.2.1.2 multiplexed status polling (msp) using four cell available signals with msp using four cell available signals, up to four cell available responses occur every two clocks. the advantage offered by the msp mode is the improved response time for phy service selection. with this method, it is possible to poll 31 devices in a single cell time. phy devices, however, must comply with this optional part of the utopia level 2 specification. a standard phy device can be configured to use this mode even though it does not support it directly. to effect this, up to eight phy devices can be configured with the addresses 0, 4, 8, 12, 16, 20, 24, and 28. figure 23 shows the receive utopia 50 mhz msp, including cell transfer. figure 24 shows the transmit utopia 50 mhz msp including cell transfer. figure 23. receive utopia multiplexed status polling (msp), including cell transfer figure 24. transmit utopia 50 mhz multiplexed status polling (msp), including cell transfer 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930 hh p h pppppppp p ppp pppppp pppp p 02 1f 1f 1f 00 04 1f 1f 08 0c 10 14 1f 1f 1f 18 1c 1f 00 30308 0 3 atm_clk ratm_data(15:0) ratm_add(4:0) /ratm_read_en ratm_clav(3:0) ratm_soc 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930 hp p p p ppppppp p ppp pppppp ppp 00 1f 1f 1f 00 04 1f 1f 08 0c 10 14 1f 1f 1f 18 1c 1f 01 0f0f08 f hh 1f h 0 atm_clk tatm_data(15:0) tatm_add(4:0) /tatm_write_en tatm_clav(3:0) tatm_soc tatm_parity
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 23 2.4.2.1.3 direct status indication using four cell available signals when configuring the device, setting the msp mode bit implicitly turns on direct status indica- tion, since it is a subset of the implemented msp method. 2.4.2.2 priority encoding and tdm table the transmit utopia selects phy devices for service based upon: ? the assigned ut priority for the phy(refer to ut_priority on page 119 ). ? the configuration of the tdm (time division multiplex) table ? per vo presence of the cells in the qengine ? cell available assertions received from the phys. the use of priority servicing is beneficial when using multi-phy configurations and the utopia bandwidth is nearly fully subscribed. 2.4.2.2.1 basic 2 level priority algorithm when tdm is disabled (refer to section 7.2.10 utopia_config) a phy device is assigned either a high or low utopia priority based of the bandwidth of the phy device. within a priority level (high or low), further control over the service algorithm can be implemented by assigning the lowest numbered phy addresses to the highest bandwidth phys. the general algorithm for deciding which phy to service is as follows: 1. the high priority encoder has highest service priority. from the high priority phys, the lowest address phy that has indicated it can accept a cell (and for which a cell is present in the qengine) is selected. if no high priority phy is selected, then the low priority set is considered next. 2. the low priority encoder has the next highest service priority. the lowest address phy that has indi- cated it can accept a cell (and for which a cell is present in the qengine) is selected. if no low priority phy is selected then the cell time is wasted unless the watchdog is configured for operation, in which case the stale priority set is considered next. the watchdog is only available on the transmit side. 3. the transmit stale priority encoder has the lowest priority and is created for the phy devices that the watchdog deems stale. the lowest address phy that has been detected dead or "stale" by the watch- dog (and for which a cell is present in the qengine) is selected. the cell is played out on the interface in order to relieve vo queue depth congestion. the watchdog plays the role of making a best effort deliv- ery, even though the phy is considered dead. caveat: service selection is performed each cell time with the clav information gathered from the previous cell time. this is particularly important, when the standard polling method is used and not all phy's can be polled in a single cell time. in this mode, utopia priorities have relative meaning within 4 address groups of 8 (0to7, 8to15, 16to24 and 25to31). for example a high prior- ity phy of address=1 will compete for service with a low priority phy of address=7, but will not compete for service against a low priority phy of address=10 since they are in different groups. it is conceivable that a low priority phy can receive as much service as a high priority phy. this could be the case if the phy at address=10 is the only phy in its address group. it will get the entire cell time bandwidth simply because there are no other phys to compete with.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 24 this problem does not exist in msp mode since all clav information is gathered in one cell time. 2.4.2.2.2 tdm and the basic 2 level priority algorithm when tdm is enabled, (refer to section 7.2.10 utopia_config and to section 7.2.12 ut_enable for configuring the tdm pool) another level is added on top of the basic 2 level priority algorithm. the tdm table has primary service priority if the utopia interface is con- figured to use the tdm feature. each cell time, the tdm pointer is advanced through the tdm pool in a round-robin fashion. when a phy is pointed to and a cell is present in the qengine for the phy, it will be selected. if a phy is selected and a cell is not present in the qengine for the phy, the selection process is deferred to the basic 2 level priority algorithm so that the cell time is not wasted. the tdm table is most useful when configurations require uniformally distributed bandwidths, such as 4xoc3 configurations. in the event that the tdm bit is not set in the utopia_config then the servicing algorithm reduces to the basic 2 level priority encoding scheme consisting of 1, 2 and 3 above. the receive side of the qrt operates in the same fashion as the transmit side with the exception of the stale priority level since there is no watchdog present in the receive side. the utopia level 2 specification is not designed to support oversubscription due to its lack of multi-priority cell presence indications. the qrt interface assumes this is the case in order to operate correctly. 2.4.2.3 independently configurable interfaces the receive and transmit sides of the utopia interface are independently configurable for either single-phy oc-12 or multi-phy operation. the rx_oc_12c_mode, tx_oc_12c_mode, and utopia_2 bits (refer to section 7.2.11 utopia_config starting on page 117 ) configure the device for such operation. this allows versatility in the types of phy environments that can be supported (for example, environments that contain high-speed, single-phy devices can be supported, as well as environments in which the qrt must perform single-chip, multi-phy to high-speed, single-phy muxing operations). this versatility is particularly helpful when interfac- ing to the pmc-sierra, inc. pm7322 rcmp-800 operations, administration, and maintenance (oam) processor, since the output of that device has an interface similar to a single-phy sat- urn interface. 2.4.2.4 output channel number insertion the transmit side of the utopia can be configured to insert the qrt output channel identifier in the hec/udf field of outgoing cells. the output channel identifier is a value used by the qrt transmit portion to identify cells of a particular cell stream as they come in from the fabric. inser- tion is configured by means of setting the utopia_config(7) register. if the configuration bit is set to 0, the utopia inserts a value of ffffh in the hec/udf field. the transmit utopia does not calculate the hec for outgoing cells.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 25 2.5 receiver operation 2.5.1 receive channel lookup the receive channel lookup uses two tables: vi_vpi_table (refer to vi_vpi_table on page 175 ) and vci_table (refer to vci_table on page 176 ) to generate a channel number for an incoming cell. the channel number in turn is used to access the channel control block (ccb), in the connection table. the ccb contains the configuration and state for the connection. figure 25 shows the method used to generate the channel number for vccs: the virtual input (vi) number and the vpi bits are used to index into a vi_vpi_table of up to 4k entries per vi. each entry contains the base address of a block in the vci_table for that vp and the size of that block. a vci_table entry contains a channel number for that vcc. on the other hand, if channel is a vpc, its vi_vpi_table contains the channel number directly (see figure 26). the number of active vc bits can be modified during operation of the qrt by creating a new vci_table and then changing the vc_base and vci_bits (refer to vci_bits on page 176 ) values to point to the new table in one write. this is possible since the block_offset (refer to block_offset on page 176 ) is just a pointer to the vci_table, and the vci_table holds no state information. thus, when the first connection arrives, the eventual size of the vci block can be initially guessed. later, if the guess proves to be too low and the table grows too big, there is no penalty: a new vci_table can be created on-the-fly. this method of determining the ccb allows a flexible and wide range of active vpi and vci bits without requiring an expensive content-addressable memory (cam) or causing fragmentation of the ccbs. figure 25. vcc channel lookup block_offset, vci_bits channel number channel control block (ccb) vpi vi_vpi_table vci_table (one table per vp) connection table vci
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 26 figure 26 shows the mapping for vpcs. figure 26. vpc channel lookup channel number channel control block (ccb) vi_vpi_tabl connection table
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 27 2.5.2 receive vc (channel) queuing receive cells are enqueued on a per-vc (channel) basis. this means that there are up to 16k queues. singly-linked lists are used to queue the cells. the head pointers, the tail pointers, and the linked lists are all in external ram. figure 27, figure 28, and figure 29 show the operation of the channel linked list structure. figure 27. channel linked list figure 28. channel linked list C a new cell arrives figure 29. channel linked list C a cell is sent to the fabric per-vc linked list channel head tail link link link per-vc linked list channel head tail link link link link per-vc linked list channel head tail link link link
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 28 2.5.3 receive channel ring the list of channels eligible to send a cell to the fabric are kept in per-sc rings. the ring is kept in external memory and pointers to the previous and current channels for each sc are kept in inter- nal memory. a channel number is entered into the ring when the first cell for that channel arrives. while cells for that channel are present in the queuing system, the channel can be removed from the ring by the dequeue process (if the channel is run-limited because of the resequencing algo- rithm as explained in receive sequencing algorithm on page 34 ) and sometimes re-added to the ring by the process that updates the data structures with the results of the last cell time. figure 30, figure 31, figure 32, and figure 33 on page 29 show the operation of the receive chan- nel ring. figure 30. receive channel ring figure 31. receive channel ring after channel_a becomes run-limited service class (sc) current channel previous channel_a channel_e channel_d channel_c channel_b service class (sc) current channel previous channel_e channel_d channel_c channel_b
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 29 2.5.4 receive congestion management the receive queue controller maintains current, congested, and maximum queue depth counts of cells on a per-vc, per-sc, and per-device basis. three congestion management algorithms are available for use on a per-channel basis. in each channels rx_ch_config word (refer to section 9.3.1.1 rx_ch_config starting on page 184 ) there are bits that enable epd, clp- based discard, and efci. these may be used in combination. in addition, ptd is supported as a mode of the epd operation. figure 32. receive channel ring after channel_b is served but it is not run-limited figure 33. receive channel ring after channel_a gets cell through fabric and is added to ring figure 34. receive congestion limits service class (sc) current channel previous channel_e channel_d channel_b channel_c service class (sc) current channel previous channel_d channel_b channel_a channel_c channel_e per service class (sc) per device (dir) per channel
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 30 a congestion hysteresis bit is kept for each threshold. this bit is set whenever the queue depth exceeds the congestion limit for that threshold. this bit remains asserted until the queue depth falls below one-half of the congestion threshold. figure 35 illustrates the operation of epd/ptd. figure 36 shows the operation of epd in combination with clp-based dropping. figure 35. epd/ptd operation figure 36. epd/ptd with clp operation drop these frames always send the last cell of each tail drop this frame time maximum threshold queue depth congested threshold congested queue depth ? 2 cells are arriving at a rate greater than the rate at which they are being played out. = end-of-frame (eof) cell drop these frames always send the last cell of each tail drop this frame time maximum threshold queue depth congested threshold congested queue depth ? 2 cells are arriving at a rate greater than the rate at which they are being played out. = end-of-frame (eof) cell = cell loss priority (clp)
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 31 figure 37 shows the operation of efci. the congestion limits are kept in an exponential form. the interpretation of the limits is the same for all measurements, except the device limit. for the other measurements, the value of 0 causes the measurement to always find congestion. the value of 1 may not be used. the value of f h causes congestion to be found for the limit when the queue depth is 31744. this allows a 15-bit value to be used to store the state of each measurement except the device measurement, which has a 16-bit value. 2.5.5 receive queue service algorithm each switch fabric cell time, the receive queue controller selects up to four cells for transmission to the switch fabric. the controller supports per-channel (per-vc) queues with 64 scs. the con- troller addresses the following issues: qos, cell delay variation (cdv) minimization, minimum cell rate (mcr) guarantees, and fairness maximization. the flexibility of the controller ensures that vcs receive their expected bandwidth in a timely fashion depending upon their traffic requirements. figure 37. efci operation figure 38. steps to send a cell to the fabric efci codepoints set from here to here time time queue depth congestion threshold congestion threshold ? 2 run queue service algorithm to determine service class (sc) read from ring to determine channel find pointer to cell from channel linked list fetch cell send cell to fabric update structures with results of transmission
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 32 the controller has a scheduler that selects cells to be placed in pipelined, ping-pong buffers. once a cell is selected, it is placed in one of these buffers. each of the four outputs to the switch fabric has two buffers: while a cell in buffer a is being transmitted, another cell is selected and placed into buffer b . on the subsequent switch fabric cell time, the buffers are ping-ponged, and the cell in buffer b is sent. meanwhile, another cell is selected for buffer a . an exception to this process is when the controller receives a negative acknowledgment (nack) for transmission of a cell. there are two cases: the nack is an mnack, indicating cell trans- mission failed due to collision in the middle of the network, or else the nack is an onack, indicating cell transmission failed due to collision at an output of the network. in the former case, the cells switch fabric priority (assigned during vc setup) is compared with that of the cell (if any) in the other ping-pong buffer. call the first cell x , and the second cell y . if the priority of cell x is greater than or equal to that of cell y , the buffers are not ping-ponged, and cell x will be resent next time. if the priority of cell x is less than that of cell y , cell x remains in its buffer, and the buffers are ping-ponged as usual, with cell y being sent next. in the latter case, the cell is requeued at the head of its vcs queue. thus, the cell will be retransmitted, but at a later time than if the cell was mnacked. the switch fabric has been specially designed to minimize the possibility of consecutive colli- sions at the same place in the middle of the network, and thus a cells transmission that failed in that manner stands a good probability of being successful in an immediately subsequent transmis- sion attempt. collisions at an output of the network are more likely to be recurring for a period of time, and thus the next transmission attempt is delayed. the scheduler that places cells in the ping-pong buffers operates as follows: the scs are arranged in a tabular fashion as seen in figure 39. an sc is designated for either unicast or multicast traf- fic. additionally, an sc is designated as either strict priority sc1, strict priority sc2, or general purpose (gp). associated with each sc is a weight of either 1, 4, 16, or 64. this information is
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 33 used by the controller to decide which sc to service. following this decision, the selected scs vcs are serviced in a round-robin manner. the selected vc then transmits the first cell in its queue. the general algorithm for deciding which sc to service is as follows (certain multicast scs may be ineligible for selection in particular modes or operating conditions; these will be described after the numbered list that follows): 1. strict priority sc1 has primary service priority. if there is an sc1 with a cell, it will be selected. the sc1 service classes are serviced in a weighted round-robin manner, alternating between unicast and multicast classes (q 0 , q 32 , q 1 , q 33 , q 2 , q 34 , q 3 , q 35 , q 0, ...). the sc1 round-robin pointer will remain pointed at an sc for up to w cell selections, where w is the scs weight. if no cells are available in an sc, the round-robin pointer is advanced. thus, the most time-critical vcs should be placed in an sc1 service class. the pointer for the sc1 service classes is separate from the pointer to the sc2 and gp ser- vice classes. 2. strict priority sc2 has secondary service priority. it is treated in the same fashion as sc1, except it has its own independent round-robin pointer and the weighted round-robin order is: q 4 , q 36 , q 5 , q 37 , q 6 , q 38 , q 7 , q 39 , q 4 , .... 3. if no cell exists in the strict priority classes, then the controller accesses the timeslot-based priority table in a round-robin manner. each entry of this table contains a gp sc number. if the sc pointed to by the active entry has cells, that sc is selected. the active entry is incremented to the next timeslot each time the timeslot table is accessed. the table has 127 entries and wraps around. this servicing mechanism provides the mcr guarantee on a per-sc basis. the number of times an sc is placed in the timeslot table can be used to determine its mcr. 4. if no cell exists in the strict priority classes, and no cell exists in the sc pointed to by the active entry of the timeslot-based priority table, then the gp scs are serviced in a weighted round-robin manner simi- lar to the sc1 and sc2 classes (q 8 , q 40 , q 9 , q 41 , q 10 , q 42 , q 11 , q 43 , q 12 , q 44 , ..., q 31 , q 63 , q 8 , ...). again this has a separate round-robin pointer than that kept for the sc1 and sc2 service classes. figure 39. receive service class (sc) map unicast traffic multicast traffic strict priority sc1 strict priority sc2 timeslot-based priority general purpose (gp) weighted round- robin scs q 0 q 2 q 3 q 1 q 4 q 6 q 7 q 5 q 32 q 34 q 35 q 33 q 36 q 38 q 39 q 37 q 8 q 10 q 11 q 9 q 40 q 42 q 43 q 41 s 0 s 1 q 12 q 14 q 15 q 13 q 44 q 46 q 47 q 45 q 16 q 18 q 19 q 17 q 48 q 50 q 51 q 49 q 20 q 22 q 23 q 21 q 52 q 54 q 55 q 53 q 24 q 26 q 27 q 25 q 56 q 58 q 59 q 57 q 28 q 30 q 31 q 29 q 60 q 62 q 63 q 61 s 125 s 126 vc 1 vc 2 vc 4 vc 3 round-robin among vcs within an sc
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 34 certain multicast scs may be ineligible for selection due to the aggregate mode and the backpres- sure from the switch fabric. the qrt can be set to a multicast aggregate mode of either 1 or 4. in aggregate mode of 1, each of the switch fabric outputs of the qrt are treated as distinct outputs. multicast connections must be specifically assigned to an sc in the corresponding column of multicast scs (there are 32 multicast scs, with four columns of eight classes each), since all the cells of a multicast vc must use the same output. in this mode, only one column (eight) of the multicast scs will be eligible for selection (for example, service classes q 32 , q 36 , q 40 , q 44 , q 48 , q 52 , q 56 , and q 60 correspond to port 0 and service classes q 33 , q 37 , q 41 , q 45 , q 49 , q 53 , q 57 , and q 61 correspond to port 1). the other three columns of scs (total of 24 scs) will be ineligible. in aggregate mode of 4, the four outputs are treated as one logical output, and thus all multicast scs may be selected for any of the four outputs. additional scs may be ineligible due to backpressure from the switch fabric. there are three types of backpressure: high, medium and low. high backpressure renders the eight sc1 and sc2 multicast scs ineligible (q 32 to q 39 ). medium backpressure renders the first eight gp scs ineligi- ble (q 40 to q 47 , two rows of four). low backpressure renders the last 16 gp scs ineligible (q 48 to q 63 , four rows of four). the receive queue controller scheduler provides the following benefits: ? qos - the strict priority scheme between sc1, sc2, and gp scs, and the weighted round- robin algorithms allow satisfaction of qos guarantees. ? cdv minimization - the treatment of the strict priority scs ensure cells within these scs get timely service. ? mcr guarantee - the timeslot table ensures all scs will receive a minimum amount of servicing (clearly, the aggregate bandwidth given to the sc1 and sc2 vcs affects the remaining bandwidth to be divided between the gp scs). ? fairness maximization - how scs (1, 4, 16, or 64) are weighted allows different scs to support different bandwidth requirements (for example, high bandwidth scs are assigned 64 and are serviced 64 times as often as low bandwidth scs, which are assigned 1). 2.5.6 receive sequencing algorithm one of the service guarantees atm offers is the fifo delivery of cells. since the qrt can send multiple cells from a channel simultaneously across the fabric, and not all of those cells will get through on the first try, the qrt must support an algorithm to make sure the cells can be put back into order. the algorithm it supports is a classic window algorithm where only n cells are allowed to be outstanding without acknowledgment. in the qrt, n is either 1 or 2. this limits the data rate of an individual connection to approximately 155 mbps. the cells are sequence numbered and reordered at the transmit side. this algorithm is implemented by removing the channel from the ring of eligible channels when- ever two cells are outstanding. the channel is then called run-limited. it also removes the channel from the ring if the last cell present has been sent to the switch fabric. the channel is then called cell-limited. in the former case, it will remain off the ring until the fabric transmission results for
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 35 a run-completing cell are known. for n = 1, every cell completes a run. for n = 2, the cell with the modulo lower sequence number (sn) is the run-completing cell. at that time it will be added back onto the ring if there are more cells to send or if that cell was onacked, in which case that cell can be resent. the pointers for these cells are stored in two locations in the ccb. when starting from no cells in the fabric, the first cell sent is always in pointer0 and the second cell is always in pointer1. for multicast and unicast cells, use n = 2. the n = 1 setting is available for use, but has lower utility than the n = 2 setting for virtually all situations. 2.6 transmitter operation 2.6.1 transmit queuing transmit cells are enqueued on a per-sc, per-vo basis. as there are 31 vos, and 16 scs per vos, there are a total of 496 queues. singly linked lists are used to queue the cells. the head and tail pointers are in internal ram and the linked lists are in external ram. figure 40 shows an example transmit per-scq linked list. 2.6.2 transmit congestion management a cell received from the switch fabric interface is queued by the transmit queue controller if it passes ten buffer threshold checks: both maximum and congested thresholds for the device, vo, sc, queue, and channel as shown in figure 41 on page 36 . the cell waits in the transmit cell buffer dram until the transmit queue controller selects it for transmit multicast/header mapping. the cell then exits the device through the utopia interface. a congestion hysteresis bit is kept for each threshold. this bit is set whenever the queue depth exceeds the congestion limit for that threshold. this bit remains asserted until the queue depth falls below one-half of the congestion threshold. the congestion limits are kept in an exponential form. the interpretation of the limits is the same for all measurements except the device limit. for the other measurements, the value of 0 causes the measurement to always find congestion. the value of 1 may not be used. the value of f h figure 40. transmit per-scq linked list per-scq linked list channel head tail vo, link link link
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 36 causes congestion to be found for the limit when the queue depth is 31744. this allows a 15-bit value to be used to store the state of each measurement except the device measurement, which has a 1-bit value. three congestion management algorithms are available for use on a per-channel basis. in each channels tx_ch_config word (refer to section 9.3.1.7 tx_ch_config starting on page 189 ) are bits that enable epd, clp-based discard, and efci. these may be used in combi- nation. in addition, packet tail discard (ptd) is supported as a mode of the epd operation. fig- ure 35 on page 30 illustrates the operation of epd/ptd. figure 36 on page 30 illustrates the operation of epd/ptd with clp. as described in transmit resequencing algorithm on page 39 , there is an interaction between epd and the resequencing algorithm. refer to that section for a complete description. 2.6.3 transmit queue service algorithm the transmit queue controller supports 16 scs for each of its 31 vos (the per-vo structure is shown in figure 42 on page 38 ). as with the receive queue controller, the transmit queue control- ler addresses the following key issues: qos, cdv minimization, mcr guarantee, fairness maxi- mization, and output isolation. figure 41. transmit maximum and congested threshold checks per service class (sc) per queue 31 virtual outputs (vos) 16 service classes (scs) per device per virtual output (vo) per channel
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 37 the vo for which a cell is to be sent is determined first by doing a bit-wise and of two vectors: one vector indicates the presence of a cell for a vo, and the other vector indicates the willingness of a vo to accept a cell. of the matching vos, the lowest numbered vo of high priority is selected if possible; otherwise, the lowest numbered vo is selected. once the vo is known, the controller has a scheduler that selects a cell to be transmitted to the utopia interface. the scheduler operates as follows: the scs are arranged in a tabular fashion as seen in figure 42 on page 38 . an sc is designated for either unicast or multicast traffic. addi- tionally, an sc is designated as either strict priority sc1, strict priority sc2, or gp. associated with each sc is a weight of either 1, 4, 16, or 64. this information is used by the controller to decide which sc to service. following this decision, the selected scs cells are serviced in a fifo manner. the general algorithm for deciding which sc to service is similar to that used by the receive queue controller, and is as follows: 1. strict priority sc1 has primary service priority. if there is an sc1 service class with a cell, it will be selected. the sc1 service classes are serviced in a weighted round-robin manner, alternating between unicast and multicast classes (q 0 , q 8 , q 0 , ...). the sc1 round-robin pointer will remain pointed at an sc for up to w cell selections, where w is the scs weight. if no cells are available in an sc, the round-robin pointer is advanced. thus, the most time-critical vcs should be placed in an sc1 service class. 2. strict priority sc2 has secondary service priority. it is treated in the same fashion as sc1, except it has its own independent round-robin pointer, and alternates: q 1 , q 9 , q 1 , .... 3. if no cell exists in the strict priority classes, then the controller accesses the timeslot-based priority table in a round-robin manner. each entry of this table contains a gp sc number. if the sc pointed to by the active entry has cells, that sc is selected. the active entry is incremented to the next timeslot each time the timeslot table is accessed. the table has 127 entries and wraps around. this servicing mechanism provides the mcr guarantee on a per-sc basis. the number of times an sc is placed in the timeslot table can be used to determine its mcr. 4. if no cell exists in the strict priority classes, and no cell exists in the sc pointed to by the active entry of the timeslot-based priority table, then the gp scs are serviced in a weighted round-robin manner simi-
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 38 lar to the sc1 and sc2 classes (q 2 , q 10 , q 3 , q 41 , q 11 , ..., q 7 , q 15 , q 2 , ...). the transmit queue controller scheduler provides the following benefits: ? qos - the strict priority scheme among sc1, sc2, and gp scs, and the weighted round- robin algorithms allows satisfaction of qos guarantees. ? cdv minimization - the treatment of the strict priority scs ensure that cells within these scs get timely service. ? mcr guarantee - the timeslot table ensures all scs will receive a minimum amount of servicing (clearly, the aggregate bandwidth given to the sc1 and sc2 vcs affects the remaining bandwidth to be divided between the gp scs). ? fairness maximization - the weights of the scs (1, 4, 16, or 64) allow different scs to support different bandwidth requirements (for example, high bandwidth scs are assigned 64 and are serviced 64 times as often as low bandwidth scs, which are assigned 1). ? output isolation - the cells of channels destined for different vos are kept in separate data structures. this helps isolate the effects of congestion on one vo from causing congestion on another vo. figure 42. transmit service class (sc) map (per vo) unicast traffic multicast traffic strict priority sc1 strict priority sc2 timeslot-based priority general purpose weighted round- robin scs q 0 q 1 q 2 s 0 s 1 q 3 q 4 q 5 q 6 q 7 s 125 s 126 vc cells are fifo-queued within an sc q 8 q 9 q 10 q 11 q 12 q 13 q 14 q 15
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 39 figure 43 illustrates the steps that are taken when playing out a cell. 2.6.4 transmit resequencing algorithm to guarantee the fifo delivery of cells, the qrt supports an algorithm to make sure the cells can be put back into order. the algorithm it supports is a classic window algorithm where only n cells are allowed to be outstanding without acknowledgment. in the qrt, n is either 1 or 2. this limits the data rate of an individual connection to approximately 155 mbps. the transmit end reorders the cells according to their sn. the resequencing of one algorithm ignores the incoming sn and accepts all cells as if their sn were correct. this can be used for multicast cells as the qse delivers them in fifo order. the resequencing of two algorithms inspects an incoming cell to determine if it has the expected sn, e . if it does, the cell is immediately processed. if it has sn e+1 , then it is stored to await the run-completing cell (that is, the cell with the original expected sn, e ). if it has neither sn e , nor sn e+1 , a recovery algorithm is started which gets the channel back into sequence. this is described in transmit recovery algorithm on page 40 . the resequencing of two algorithms interacts with epd. when a cell is missing, the algorithm cannot determine if the missing cell is an end-of-frame (eof) cell. it is then necessary to defer the choice of whether or not to send both cells until the run-completing cell is received. the figure 43. cell playout steps figure 44. transmit resequencing operation find pointer to cell from linked list play out cell and update channel state read outchan from cell buffer fetch cell determine vo run queue service algorithm to determine the service class (sc) cell onacked cells arrive at receive utopia cells are numbered and sent across the fabric cells are sent from transmit utopia 3 4 46 5
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 40 choice of whether or not to send or drop one or more of the cells is affected by the eof informa- tion, because one frame that is being dropped may end, and another frame that is not to be dropped may start. 2.6.5 transmit recovery algorithm no recovery algorithm is needed for the resequencing of one algorithm since the sn is ignored. for resequencing of two algorithms, when a cell with sn s is received, and s is neither equal to the expected cell number e , nor equal to e+1 , then the cell is dropped. the new expected sn (for the next cell) is set at s + 1. the next time two consecutive cells are received in ascending sn order, the channel will have recovered its sequence. using this algorithm, some legitimate cells may be dropped while recovering. for example, if the next two cells are legitimate, but are received in descending sn order, they will both be dropped. 2.6.6 transmit multicast cell background process the transmit multicast background process traverses the linked list for that channel and prepares a list of pointers to cells and pointers to headers for multicast cells. this allows the dequeue process to replicate the cell with new headers to each entry in the linked list. this is necessary because multicast cells are bound to different destinations and need different headers. figure 45 shows the replication process that occurs, according to how the fields in the mc_list word are set. figure 45. multicast background process multicast cell is available in the input fifo. look up the next_mc_header_ptr entry in the tx_channel_table pointed to by the out_chan. 1 make an entry for the cell in the output fifo for that sc on the indicated vo. increment the mc_count state bit. check replicate_cell bit. 1 0 look up the next_mc_add in the multicast control block. 1 0 move the head pointer in the input fifo and clear enq_pend state bit.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 41 figure 46 shows the operation of the multicast pointer fifos. when a multicast cell arrives, it is immediately stored to ram. the pointer to that cell buffer and the outchan for that cell are put onto one of eight input fifos. there is one fifo per input multicast sc. a background pointer replication process which runs at the utopia rate copies pointers from the input fifos to the output fifos. it does so by traversing the linked list for that outchan and copying the pointer to the cell buffer to the output fifo for that sc on the proper vo. the background process dynamically identifies if any of the output fifos are full. if any become full, the process records which vos are full for that sc and ceases transferring cells for that sc. transfers still are free to occur for other scs. once the dequeue process serves a cell instance from that sc on the bottlenecked vo, the background process is free to continue to do replica- tions for that sc. the background process runs at exactly the same rate as the utopia interface. this allows it to transmit multicast cells at the full rate out of the interface, even if each multicast cell is only going to one destination on this qrt. figure 46. multicast pointer fifo operation channel ram linked list sdram background pointer replication process 31 8 per-sc, per-vo output pointer fifos eight per-sc input pointer fifos = cell header translation flow = cell pointer control flow cell pointer , channel # cell header cell cell pointer = cell payload flow
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 42 2.6.7 transmit multicast congestion management the transmit multicast can have congestion management applied to it. three of the five conges- tion measurements apply: the device, the sc, and the channel. the vo and the sc queue limits do not apply to multicast cells as they do not make sense. this is because only one copy of the cell is kept in the dram, regardless of the number of destinations to which the cell is headed. those counts contain only the number of unicast cells present. the qrt can be configured to either generate or not generate backpressure on a per-sc basis. if no backpressure is desired, configure tx_exp_max_sc_qd (refer to tx_exp_max_sc_qd on page 163 ) to one-half of the input pointer fifo depth for that al_ram_config (refer to al_ram_config on page 105 ). this will drop all cells at a depth deeper than this, preventing backpressure from reaching back into the switch fabric. the setting of this is a system-level decision. preventing backpressure prevents a failure or congestion on one card from affecting the performance of the fabric as a whole. on the other hand, using the backpressure allows more multicast cells to be passed without the fear of dropping in the egress qrt. the high priority backpressure bit is derived from the near-fullness of queues 8 and 9. the medium priority backpressure bit is derived from the near-fullness of queue 10 and 11. the low priority backpressure bit is derived from the or of the near-fullness of queues 12 to 15. epd, clp-based dropping, and efci are all valid for multicast cells and are configured in the tx_ch_config word (refer to section 9.3.1.7 tx_ch_config starting on page 189 ) using the same bits as for unicast connections.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 43 2.7 system diagram of internal qrt blocks and external ram figure 47 shows a system diagram of the internal qrt blocks and the external ram. figure 47. system diagram of internal qrt blocks and external ram 50 mhz 100 mhz 66 mhz 50 mhz 100 mhz 66 mhz receive utopia transmit utopia to qse from qse bp/ack from qse bp/ack to qse tx dram control tx dram cell buffer mc ram tu ram tsc ram tsf ram ts ram vo ram queue engine ch ram control ch ram al ram al ram control utopia loopback rsc ram rsf ram rs ram abr ram control receive dram control ru ram microprocessor interface microprocessor rx dram cell buffer abr ram
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 44 3 fault tolerance 3.1 the data path figure 48 shows the basic data path through the switch. the se_d_out/in and se_soc_out/ in signals are used in the forward path, and the bp_ack_out/in signals are used in the back- ward path. data enters the switch via the ingress or receive side utopia interface and is queued at the input half of the qrt (the irt). the receive queue controller selects cells that are then played out to the switch fabric, which consists of one or more stages of qses. the cell finally enters the egress qrt where it is queued again at the output half of the qrt (the ort). the transmit queue controller selects a cell which is then played out of the switch via the egress or transmit side utopia interface. 3.1.1 utopia interface the qrt utopia interface is compatible with the utopia level 1 specification revision 2.01 and the utopia level 2 specification in 16-bit mode with cell-level handshaking. an external atm clock must be provided to this interface with a frequency between 15 mhz and 50 mhz. the lower bound is determined by the atm_clk failure detection circuitry. the receive and transmit sides of the interface are independently configurable to operate in either single oc-12 or multi-phy fashion. the interface also provides several options in polling methods, so bandwidth, servicing fairness, and response time are optimized for any given phy layer device arrangement. figure 48. basic data path through the switch a b c d a b c d e f e f g h g h e f e f c d c d qrt (irt portion) a qrt (irt portion) b qse/qse interface qrt (ort portion) a qrt (ort portion) b forward cell path backward bp/ack path qse (switching matrix) qse (switching matrix) qse/qrt interface qrt/qse interface utopia interface utopia interface
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 45 3.1.2 switch fabric interface the switch fabric interface of the qrt has four nibble-wide, 50 or 66 mhz interfaces with back- pressure to interface to qses (pm73488s). the device can avoid head-of-line blocking by receiv- ing two forms of negative acknowledgment from the switch fabric. one form of negative acknowledgment indicates congestion that is likely to be resolved on the next cell time. this is termed a mid-switch nack (or medium negative acknowledgment - mnack). when the qrt receives an mnack, it resends the same cell. the other form of negative acknowledgment indicates congestion that is not likely to be resolved on the next cell time. this is termed output negative acknowledgment (onack). when the qrt receives an onack, it skips to another channel and sends a cell from that different channel. 3.2 fault detection and isolation the data transfers internally between the various rams and between the qrt and the qse are checked by the following mechanisms: ? memory parity checking ? utopia interface fault detection and recovery mechanisms ? switch fabric fault detection and recovery mechanisms 3.2.1 memory parity checking the receive and transmit buffer sdrams are checked by multibit parity. all external srams have parity checking. the parity conditions are checked. there are two kinds of flags (sticky and non-sticky) set for each of these parity error conditions. the sticky error bits are set by the error and are cleared by the processor. the corresponding non-sticky bits are used for debugging purposes. 3.2.2 utopia interface fault detection and recovery mechanisms the qrt uses several mechanisms to ensure cell integrity through the utopia interface and to expediently detect, isolate, and rectify fault conditions. 3.2.2.1 header error check (hec) the receive or ingress utopia interface can be configured to perform a hec calculation using the chk_hec bit in the utopia_config register (refer to section 7.2.11 utopia_config starting on page 117 ). when a hec failure is detected and checking is enabled, an interrupt is signaled at the processor interface and the cell is dropped at the utopia interface. some segmentation and reassembly (sar) and physical layer (phy) devices do not produce the correct hec or use the hec for other purposes. to connect the qrt to these devices, clear the chk_hec bit. 3.2.2.2 start of cell (soc) recovery the receive utopia interface is flexible when dealing with the soc signal sent from the phy layer device to the qrt. the qrt can accept a delay of up to four atm clock cycles in the aligned soc and data signals after assertion of the receive utopia atm
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 46 layer enable signal (/ratm_read_en). the soc signal can arrive anywhere within this window and the data will be accepted. customers will find this feature useful if glue logic is used for special phy layer device adaptations. if, however, the soc signal arrives after the four-cycle window, the qrt will dump the cell and enter recovery mode. recov- ery mode is implemented for both single and multi-phy configurations and provides robustness to the qrt in the event of a late soc resulting from a reset phy or a double soc resulting from renegade phy devices. the recovery mode performs precession in the atm cell cycles that follow. this is necessary to bring a phy device back into syn- chronization for slotted cell-level handshaking. soc recovery performs the same func- tions for stuck-at faults in the soc signal. when an soc failure is detected, an interrupt is signaled at the processor interface. 3.2.2.3 transmit watchdog the qrt transmit or egress utopia interface has a function called the watchdog. the watchdog exists to protect the qrt vo queues from overflow if a phy sink goes offline or stops requesting cells. the watchdog can be configured in the utopia_config reg- ister in the processor interface (refer to wd_time on page 118 ). the watchdog can be turned off or set to tolerate either oc-3-, ds1-, or ds0-level outputs. the watchdog oper- ates by observing the liveliness of the transmit utopia atm layer cell available sig- nals (tatm_clav(3:0)). if the qrt determines a phy device has stopped accepting cells, the cells intended for that phy device are played out. otherwise, if the phy device can accept these cells and the tatm_clav(3:0) signal dormancy is due to a stuck-at fault, normal utopia signaling at the lowest priority occurs whenever spare bandwidth is available. 3.2.2.4 transmit parity the transmit utopia interface performs utopia level 2 odd parity calculation over the transmit utopia atm layer data signals (tatm_data(15:0)) for the phy devices to use in error checking. 3.2.2.5 atm clock failure detection the utopia interface contains an atm clock failure detection circuit. the detection cir- cuit samples the atm clock with the high-frequency system clock and determines if the atm clock possess signal changes. if the clock failure detection circuit is tripped, an interrupt is signaled at the processor interface. 3.2.2.6 receive cell available signal stuck at 1 when a phy interface devices cell available signal is stuck at 1, the receive utopia level 2 interface limits the phy to approximately one-half the receive side qrt band- width. this condition can result from a floating cell available line and should be avoided by designing pull-down resistors for the cell available lines. in the transmit direction, this is not such an issue, because the cell service is dependent on the presence of a cell bound for that phy device. however, this condition should be minimized in the transmit direc- tion also.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 47 3.2.2.7 highest bandwidth device support in utopia level 2 mode the qrt utopia level-2 50 mhz interface was not designed to operate with any device possessing a bandwidth greater than that of an oc-3. for higher bandwidth requirements, the user must use the single-phy utopia level-1 mode of operation. 3.2.3 switch fabric fault detection and recovery mechanisms the qrt uses several mechanisms to ensure cell integrity through the switch fabric and to expe- diently detect, isolate, and rectify fault conditions. 3.2.3.1 soc coding soc coding a special background pattern 0000111100001... is generated on the soc at the ingress qrt and is propagated by the qse. this background pattern is checked at the egress qrt. if this pattern is inconsistent or missing, the forward cell path is declared bad and the se_input_port_fail interrupt (refer to se_input_port_fail on page 112 ) is asserted. 3.2.3.2 soc inversions the soc is indicated by an inversion of the background pattern. also, the pattern is reset so a valid soc will always be followed by 000011110000.... this pattern reset is checked by the egress qrt, and if it is inconsistent, the forward path is declared bad and the se_input_port_fail interrupt (refer to se_input_port_fail on page 112 ) is asserted. 3.2.3.3 redundant cell present coding the first nibble of each valid cell has a predetermined format. this format is checked as the cell is received at the egress qrt. if the format is inconsistent, the forward cell path is declared bad and the se_input_port_fail interrupt (refer to se_input_port_fail on page 112 ) is asserted. this also increases the robustness of the cell presence detection, preventing an all-1s input from creating cells. 3.2.3.4 idle cell pattern checking an idle cell at the ingress qrt has a predetermined format. this pattern is checked at the egress qrt when the idle cell is received. if the format is inconsistent, the forward cell path is declared bad and the se_input_port_fail interrupt (refer to se_input_port_fail on page 112 ) is asserted. 3.2.3.5 dropping cells with bad header parity odd parity is generated over the first 12 nibbles of every valid cell. the parity bit is embedded in the twelfth nibble. parity checking can be disabled by asserting the parity_fail_dis bit (refer to parity_fail_dis on page 107 ). when parity checking is enabled, cells with bad parity are dropped and a failure is reported to the microprocessor via the tx_parity_fail flag (refer to tx_parity_fail on page 111 ).
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 48 3.2.3.6 forced bad parity the header parity detection logic can be checked by clearing the p bit in the rx_ch_tag word (refer to rx_ch_tag on page 185 ). this forces bad parity (even parity) to be created. 3.2.3.7 marked cell counting the mark bit (mb) in the rx_ch_tag word (refer to rx_ch_tag on page 185 ) is set and it is sent between the qrt and qse. if ack or no_resp feedback is received, the rx_marked_cells counters count enabled cells (modulo 16) at the ingress qrt. the tx_marked_cells counters count marked cells (modulo 16) that are received at the egress qrt. the rx_marked_cells and tx_marked_cells counters (refer to marked_cells_count on page 110 ) help identify subtle failures in the fabric and can be used to create strong diagnostic routines. these counters are separate for all four switch fabric interfaces in each of the transmit and receive directions. 3.2.3.8 remote data path failure indication when a cell path is determined to be bad, the egress qrt indicates a remote failure by violating the syntax of the bp_ack_out signal. this is an indication to the ingress qrt that a fabric fault in the forward cell path has been detected. also, an se_input_port_fail interrupt (refer to se_input_port_fail on page 112 ) is flagged to the microprocessor. the cell being received at this time is discarded. this is detected as a bp_remote_fail (refer to bp_remote_fail on page 112 ) by the qrt or qse on the other end of the link. withholding backpressure from the ingress qrt prompts it to send only idle cells on the forward cell path until it recognizes a valid back- pressure pattern again. 3.2.3.9 unacknowledged cell detection if no acknowledgment is received for a cell, the ack_live_fail interrupt (refer to ack_live_fail on page 111 ) is asserted. this is an indication of a problem in the end-to-end path through the switch fabric. 3.2.3.10 switch fabric loopback the internal loopback feature also helps detect and isolate fabric faults. when dribbling errors or other faults are detected, internal loopback can help isolate the fault. 3.2.3.11 fabric clock failure detection the switch fabric interface contains a clock failure detection circuit. the detection circuit samples the fabric clock with the high-frequency system clock and determines whether or not it possess signal changes. if the clock failure detection circuit is tripped, an interrupt is signaled at the processor interface. 3.2.3.12 liveness of backpressure signal the backpressure signal is checked for a 10 pattern at the start of the backpressure sig- nal. for each of the qses, the qrt has a backpressure (bp) liveness indication bit called bp_ack_fail (refer to bp_ack_fail on page 112 ). there are two bits per qse
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 49 port called ack_live_fail and bp_remote_fail (refer to ack_live_fail and to bp_remote_fail on page 112 ) that check the ack response from the switch fabric and the liveness of the data line. the liveness signal alone will not determine that a qse is faulty. 3.2.3.13 bp_ack_in pattern checking backpressure and acknowledgment are transmitted from the egress qrt to the ingress qrt in packets on the bp_ack_out line. the format of the packets is as follows: a background pattern 0000111100001. . . generated by the qrt at egress and propagated by the qse. this pattern is checked at the ingress qrt. first inversion (of the background pattern) indicates the beginning of the packet. mode indicates the nature of the packet (that is, acknowledge or backpressure). data1 indicates the most significant bit (msb) of data. data0 indicates the least significant bit (lsb) of data for acknowledgment - the second bit of data for backpressure. second inversion verify the first inversion was not a glitch and the fabric is not stuck. code ext1 the lsb of the backpressure data; otherwise, it must be 0 for acknowledgment to be accepted as valid. code ext0 must be 0 to be accepted as valid. this is reserved for future use. if any part of the coding is missing or inconsistent, the bp/ack path is indicated as bad by asserting the bp_ack_fail interrupt (refer to bp_ack_fail on page 112 ). 3.2.3.14 bp_ack inversion checking the first inversion and the second inversion in the packet are separated by three bits to ensure a fabric fault, such as stuck at 1 or 0, or a glitch will not result in a false packet. if the second inversion is not consistent (inverse) with the first inversion, a bad path is indicated by asserting the bp_ack_fail interrupt (refer to bp_ack_fail on page 112 ). when the bp/ack path is determined to be bad, the ingress qrt withholds issuing valid cells and instead transmits idle cells until the fabric recovers from the fault.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 50 3.2.3.15 bp_ack remote failure detection a missing or corrupted (bad second inversion) backpressure packet is reported to the microprocessor by the bp_remote_fail flag (refer to bp_remote_fail on page 112 ). the bp_remote_fail flag is an indication of a broken cell path at the ingress qrt. a missing or corrupted acknowledgment packet is reported to the micropro- cessor by the ack_live_fail (refer to ack_live_fail on page 111 ). 3.2.3.16 detection hysteresis if the fault detected is the result of a missing or bad background pattern, it takes the qrt a minimum of 8 and a maximum of 12 switch fabric clocks to recover after the pattern has been restored. if a backpressure packet is withheld or detected as bad during a cell time because of built-in hysteresis, it takes two valid backpressure packets in successive cell times for the qrt to recover. if an acknowledgment packet is detected as bad, it takes one cell time for the qrt to recover. 3.2.4 tables of switch fabric interface failure behaviors 3.2.4.1 irt-to-switch fabric interface in figure 48 on page 44 , the irt interface consists of a and b . in the figure, a refers to each of the four se_soc_out and se_d_out#(3:0) data ports, while b refers to the corresponding bp_ack_in signals in the qrt. table 2 summarizes the failure conditions detected by the irt on b and the actions taken. table 2. failure conditions, irt-to-switch fabric interface fault detected on b action taken comment cannot lock to special coding and guaranteed transitions on bp_ack_in. idle cells are sent out on data interface a . internally to the irt, cells that would have gone out are acked if all ports are failing; else they are onacked. no multicast cells are generated for the port. bp_ack_fail (refer to bp_ack_fail on page 112 ) signaled to the microprocessor. port treated as dead. problem is probably with the bp_ack_in line. no backpressure received on bp_ack_in. idle cells are sent out on data interface a . inter- nally to the irt, cells that would have gone out are acked if all ports fail; else they are onacked. no multicast cells are generated for the port. bp_remote_fail (refer to bp_remote_fail on page 112 ) signaled to the microprocessor. port treated as dead. problem is with the forward data flow, and the qse is signaling this back to the irt. no ack, mnack, or onack received, although unicast cell is sent out. cell that was transmitted is treated as sent. ack_live_fail (refer to ack_live_fail on page 111 ) signaled to the microprocessor.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 51 3.2.4.2 qse interface, receive data direction in figure 48 on page 44 , a qse receive interface consists of c and d . in the figure, c refers to each of the four se_soc_in and se_d_in#(3:0) data ports, while d refers to the corresponding bp_ack_out signals in the qse. table 3 summarizes the failure conditions detected by the ort on c and the actions taken. table 3. failure conditions, qse receive interface fault detected on c action taken comment cannot lock to special coding and guaranteed transitions on se_soc_in. no backpressure sent out on d . all data dis- carded. se_input_port_fail (refer to se_input_port_fail on page 112 ) signaled to the microprocessor. withholding backpressure on d signals to the previous stage that the port should not be used. invalid cell present coding on se_d_in#(3:0). no backpressure sent out on d . all data dis- carded. se_input_port_fail signaled to the microprocessor. probably due to unconnected input lines that are pulled up or down. withholding backpressure on d signals to the previous stage that the port should not be used. bad idle cell coding on se_d_in#(3:0). no backpressure sent out on d . all data dis- carded. se_input_port_fail signaled to the microprocessor. withholding backpressure on d signals to the previous stage that the port should not be used. parity fail. onack sent out on d for unicast data. mul- ticast data dropped. parity_error (refer to the qse long form data sheet ) signaled to the microprocessor. the qse does not necessarily have time to drop the cell by the time it has detected a parity error.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 52 3.2.4.3 qse interface, transmit data direction in figure 48 on page 44 , a qse transmit interface consists of e and f . in the figure, e refers to each of the 32 se_soc_out and se_d_out#(3:0) data ports, while f refers to the corresponding bp_ack_in signals in the qse. table 4 summarizes the failure conditions detected by the qse on f and the actions taken. 3.2.4.4 switch fabric-to-ort interface in figure 48 on page 44 , an ort interface consists of g and h . in the figure, g refers to each of the four se_soc_in and se_d_in#(3:0) data ports, while h refers to the corresponding bp_ack_out signals in the qrt. table 5 summarizes the failure conditions detected by the ort on g and the actions taken. table 4. failure conditions, qse transmit interface fault detected on f action taken comment cannot lock to special coding and guaranteed transitions on bp_ack_in. idle cells sent out on data interface e . if possible, data routed around port. multicast data is dropped if all possible port choices are dead or off. unicast data is optionally dropped if all pos- sible port choices are dead or off. bp_ack_fail (refer to bp_ack_fail on page 112 ) signaled to the microprocessor. port treated as dead. problem is probably with the bp_ack_in line. no backpressure received on bp_ack_in. idle cells sent out on data interface e . if possible, data routed around port. multicast data is dropped if all possible port choices are dead or off. unicast data is optionally dropped if all pos- sible port choices are dead or off. bp_remote_fail (refer to bp_remote_fail on page 112 ) signaled to the microprocessor. port treated as dead. problem is with the forward data flow. no ack, mnack, or onack received, although the cell sent out is not currently monitored in the qse. no action taken. lack of ack, mnack, or onack is not monitored by the qse. table 5. failure conditions, switch fabric-to-ort interface fault detected on g action taken comment cannot lock to special coding and guaranteed transitions on se_soc_in. no backpressure sent out on h . all data dis- carded. se_input_port_fail (refer to se_input_port_fail on page 112 ) signaled to the microprocessor. withholding backpressure on h signals to the previous stage that the port should not be used. invalid cell present coding on se_d_in#(3:0). no backpressure sent out on h . all data dis- carded. se_input_port_fail signaled to the microprocessor. probably due to unconnected input lines that are pulled up or down. withholding backpressure on h signals to the previous stage that the port should not be used. bad idle cell coding on se_d_in#(3:0). no backpressure sent out on h . all data dis- carded. se_input_port_fail signaled to the microprocessor. withholding backpressure on h signals to the previous stage that the port should not be used.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 53 3.2.4.5 types of failures and their manifestations table 6 shows possible faults, their effects, and how they affect the network. parity fail. ack sent out on h . parity errored cell dropped. tx_parity_fail (refer to tx_parity_fail on page 111 ) sig- naled to the microprocessor. ack already sent by the time the qrt has detected a parity error. in this case, a cell that was dropped was acked. table 6. faults and effects on the network fault manifestation effect on network wire connection data line from se_d_in#(3:0) stuck at 0 or 1. invalid idle cell, cells with missing cell present and parity error. port shut down ( interrupt gener- ated and backpressure withheld) on receipt of first 2 consecutive bad idle cells until condition is fixed, as port failure is sent to the source of data by lack of backpres- sure indication. if only one bad idel cell received, due to the round-trip delay between the qrt and the qse, the source could send another (user) cell, causing the destination (qrt) to come out of the shut down state. this means the raw interrupt at qrt (se_input_port_fail) will be asserted and deasserted. the lateched interrupt (se_input_port_fail_latc h) will still be asserted. se_soc_in(3:0) line stuck at 0 or 1. loss-of-lock on special cod- ing on se_soc_in(3:0). port shut down until condition is fixed, as port failure is sent to the source of data by lack of backpres- sure indication. bp_ack_in(3:0) line stuck at 0 or 1. loss-of-lock on special cod- ing on bp_ack_in(3:0). port shut down until condition is fixed. bridging fault within a port. invalid idle cell with some 10/01 fail or parity error. port shut down on receipt of first bad idle cell until condition is fixed, as port failure is sent to the source of data by lack of backpres- sure indication. table 5. failure conditions, switch fabric-to-ort interface (continued) fault detected on g action taken comment
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 54 qrt and qse port failures no se_soc_out generation. loss-of-lock on special cod- ing on se_soc_in(3:0). port shut down until condition is fixed, as port failure is sent to the source of data by lack of backpres- sure indication. no data or invalid data generated. invalid idle cell with some 10/01 fail or parity error. port shut down on receipt of first bad idle cell until condition is fixed, as port failure is sent to the source of data by lack of backpres- sure indication. no bp_ack_out(3:0) generation. loss-of-lock on special cod- ing on bp_ack_in(3:0). port shut down until condition is fixed. qse chip fail- ures multicast handling. cell loss or generation. detection possible using marked cell count. multicast cell pool buffer. parity error in header or cell. detection only in header; not in payload. partial cell buffers. parity error in header and cell. parity error. multicast and unicast selection net- works. cell gets out on wrong port, cell duplicated, or cell lost. cell to wrong port may be noticed by receiving qrt, if that vc is not active. cell duplication and cell loss detection possible using marked cell count. arbiter. cell lost. detection possible using marked cell count. table 6. faults and effects on the network (continued) fault manifestation effect on network
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 55 4 pin descriptions 4.1 package diagram figure 49 (parts 1 and 2) shows the 503-pin enhanced plastic ball grid array (epbga) package used for the qrt. the package measurements are shown in millimeters. figure 49. 503-pin epbga top and side views (part 1 of 2) 40.00 0.20 40.00 0.20 measurements are shown in millimeters. not drawn to scale. PM73487-pi notes: 1. l_______b is the wafer batch code. 2. lyyww is the assembly date code. 3. dimensions are for reference. 4. controlling dimension: millimeter. 5. // = parallelism tolerance. 6. if you need a measurement not shown in this figure, contact pmc-sierra. l2a0961 l_______b 26.00 max. 26.00 max. lyyww qrt 0.86 0.15 0.25 0.10 // c c 0.60 0.10 2.98 max. 1.14 0.125 pmc-sierra, inc. pmc-sierra, inc. pmc-sierra, inc.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 56 figure 49. 503-pin epbga bottom view (part 2 of 2) notes: 1. controlling dimension: millimeter. 2. = regardless of feature size. 3. pcb material: high temperature glass/epoxy resin cloth (that is, driclad, mcl-679, or equivalent). solder resist: photoimagable (that is, vacrel 8130, dsr3241, psr4000, or equivalent). 4. if you need a measurement not shown in this figure, contact pmc-sierra. aj ah ag af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 35.56 measurements are shown in millimeters. not drawn to scale. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 40.00 0.20 40.00 0.20 1.27 35.56 45 2.8 0. 25 0.30 0.10 s s c c s a b s s 0.75 0.15
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 57 4.2 signal locations table 7. signal locations ball signal name ball signal name ball signal name ball signal name ball signal name a1 (key) b1 vss c1 vdd d1 vss e1 vss a2 vss b2 vdd c2 abr_ram_ad( 4) d2 abr_ram_ad( 7) e2 abr_ram_ad( 12) a3 vdd b3 jtag_tdo c3 /reset d3 abr_ram_ad( 2) e3 abr_ram_ad( 6) a4 vss b4 jtag_tdi c4 /jtag_reset d4 /test_mode e4 abr_ram_ad( 0) a5 vdd b5 jtag_tck c5 jtag_tms d5 /oe e5 vdd a6 /cs b6 /intr c6 pclk d6 stats_strb e6 vss a7 vss b7 addrdata(30 ) c7 /ads d7 /ready e7 /scan_en a8 vss b8 addrdata(31 ) c8 addrdata(28 ) d8 addrdata(27 ) e8 w_/rd a9 vss b9 addrdata(20 ) c9 addrdata(21 ) d9 addrdata(29 ) e9 addrdata(24 ) a10 vdd b10 addrdata(22 ) c10 addrdata(25 ) d10 addrdata(23 ) e10 addrdata(26 ) a11 vdd b11 addrdata(12 ) c11 addrdata(19 ) d11 addrdata(15 ) e11 addrdata(17 ) a12 vss b12 addrdata(11 ) c12 addrdata(14 ) d12 addrdata(10 ) e12 addrdata(18 ) a13 addrdata(6) b13 addrdata(8) c13 addrdata(9) d13 addrdata(13 ) e13 addrdata(16 ) a14 vdd b14 addrdata(5) c14 addrdata(7) d14 addrdata(3) e14 addrdata(2) a15 vss b15 addrdata(1) c15 addrdata(4) d15 ratm_data(1 5) e15 addrdata(0) a16 vdd b16 sys_clk c16 ratm_data(9 ) d16 ratm_data(6 ) e16 ratm_data(2 ) a17 ratm_data(1 4) b17 ratm_data(1 3) c17 ratm_data(1 2) d17 ratm_data(1 0) e17 ratm_data(1 ) a18 vss b18 ratm_data(1 1) c18 ratm_data(4 ) d18 ratm_data(5 ) e18 ratm_data(3 ) a19 vdd b19 ratm_data(7 ) c19 ratm_add(4) d19 ratm_addr(0 ) e19 ratm_clav(2 ) a20 vdd b20 ratm_data(8 ) c20 / ratm_read_ en d20 ratm_clav(0 ) e20 ratm_add(1) a21 vss b21 ratm_add(2) c21 ratm_add(3) d21 ratm_soc e21 rx_dram_da ta(30) a22 vss b22 ratm_data(0 ) c22 ratm_clav(3 ) d22 rx_dram_da ta(29) e22 rx_dram_da ta(25)
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 58 a23 vss b23 rx_dram_da ta(31) c23 rx_dram_da ta(26) d23 rx_dram_da ta(23) e23 rx_dram_da ta(16) a24 ratm_clav(1 ) b24 rx_dram_da ta(28) c24 rx_dram_da ta(24) d24 rx_dram_da ta(20) e24 rx_dram_da ta(18) a25 vss b25 rx_dram_da ta(27) c25 rx_dram_da ta(21) d25 rx_dram_da ta(15) e25 vdd a26 vss b26 rx_dram_da ta(22) c26 rx_dram_da ta(17) d26 vss e26 rx_dram_da ta(11) a27 vdd b27 rx_dram_da ta(19) c27 rx_dram_da ta(14) d27 rx_dram_da ta(8) e27 rx_dram_da ta(9) a28 vss b28 rx_dram_da ta(12) c28 rx_dram_da ta(10) d28 rx_dram_da ta(7) e28 rx_dram_da ta(5) a29 vdd b29 vss c29 vdd d29 vss e29 vss table 7. signal locations (continued) ball signal name ball signal name ball signal name ball signal name ball signal name
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 59 f1 / abr_ram_we k25 rx_dram_ad d(6) p1 vdd u25 se_soc_in(0) aa 1 vss f2 abr_ram_ad( 13) k26 rx_dram_ad d(2) p2 ch_ram_dat a(0) u26 bp_ack_out( 1) aa 2 ch_ram_dat a(18) f3 abr_ram_ad( 9) k27 / rx_dram_ra s p3 ch_ram_add (9) u27 bp_ack_out( 3) aa 3 ch_ram_dat a(19) f4 abr_ram_ad( 5) k28 rx_dram_ad d(0) p4 ch_ram_add (6) u28 bp_ack_in(1) aa 4 ch_ram_dat a(27) f5 abr_ram_ad( 3) k29 vdd p5 ch_ram_add (2) u29 bp_ack_in(2) aa 5 ch_ram_dat a(22) f25 rx_dram_da ta(6) l1 vdd p25 se_d_out0(3) v1 vss aa 25 se_d_in0(2) f26 rx_dram_da ta(3) l2 ch_ram_add (7) p26 se_d_out1(1) v2 ch_ram_dat a(10) aa 26 se_clk f27 rx_dram_da ta(1) l3 /ch_ram_we1 p27 se_d_out1(0) v3 ch_ram_dat a(13) aa 27 se_d_in3(1) f28 rx_dram_ad d(7) l4 / ch_ram_ads c p28 se_d_out1(2) v4 ch_ram_dat a(9) aa 28 se_d_in3(2) f29 rx_dram_da ta(2) l5 /abr_ram_oe p29 vdd v5 ch_ram_dat a(16) aa 29 vss g1 vss l11 vss r1 vss v25 se_soc_in(1) ab1 vss g2 abr_ram_ad( 16) l13 vss r2 ch_ram_dat a(4) v26 se_soc_in(3) ab2 ch_ram_dat a(29) g3 abr_ram_ad( 11) l15 vss r3 ch_ram_add (16) v27 atm_clk ab3 ch_ram_dat a(26) g4 abr_ram_ad( 8) l17 vss r4 ch_ram_add (15) v28 bp_ack_out( 0) ab4 ch_ram_dat a(25) g5 abr_ram_ad( 1) l19 vss r5 ch_ram_add (17) v29 vdd ab5 ch_ram_dat a(31) g25 rx_dram_da ta(13) l25 dram_cke r11 vss w1 vdd ab2 5 tx_dram_da ta(31) g26 rx_dram_da ta(4) l26 se_d_out3(3) r13 vss w2 ch_ram_dat a(11) ab2 6 se_d_in0(3) g27 rx_dram_da ta(0) l27 se_soc_out w3 ch_ram_dat a(17) ab2 7 se_d_in1(3) g28 rx_dram_ad d(5) l28 se_d_out3(0) r17 vss w4 ch_ram_dat a(14) ab2 8 se_d_in1(0) g29 vss l29 vdd r19 vss w5 ch_ram_pari ty0 ab2 9 vss h1 vss m1 vss r25 se_d_out0(1) w1 1 vss ac1 vss table 7. signal locations (continued) ball signal name ball signal name ball signal name ball signal name ball signal name
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 60 h2 ch_ram_add (0) m2 ch_ram_add (11) r26 se_d_out0(0) w1 3 vss ac2 ch_ram_dat a(28) h3 / abr_ram_ad v m3 ch_ram_add (4) r27 bp_ack_in(3) w1 5 vss ac3 ch_ram_dat a(30) h4 abr_ram_ad( 14) m4 ch_ram_add (5) r28 se_d_out0(2) w1 7 vss ac4 /alram_adsc h5 abr_ram_ad( 10) m5 ch_ram_add (3) r29 vss w1 9 vss ac5 alram_add(4 ) h25 / rx_dram_cs( 1) m25 / rx_dram_ca s t1 vdd w2 5 se_d_in2(0) ac2 5 tx_dram_da ta(22) h26 rx_dram_ad d(4) m26 se_d_out2(2) t2 ch_ram_dat a(6) w2 6 se_d_in2(3) ac2 6 tx_dram_da ta(27) h27 / rx_dram_we m27 se_d_out2(0) t3 ch_ram_dat a(3) w2 7 se_d_in3(3) ac2 7 tx_dram_da ta(30) h28 / rx_dram_cs( 0) m28 se_d_out3(1) t4 ch_ram_dat a(2) w2 8 rx_cell_sta rt ac2 8 se_d_in0(1) h29 vss m29 vss t5 ch_ram_dat a(1) w2 9 vdd ac2 9 vdd j1 vss n1 ch_ram_add (14) t25 se_soc_in(2) y1 vdd ad 1 alram_clk j2 /ch_ram_oe n2 ch_ram_add (13) t26 proc_mon y2 ch_ram_dat a(20) ad 2 alramadd18 n j3 /ch_ram_we0 n3 ch_ram_add (12) t27 bp_ack_out( 2) y3 ch_ram_dat a(23) ad 3 ch_ram_pari ty1 j4 / abr_ram_ad sp n4 ch_ram_add (10) t28 bp_ack_in(0) y4 ch_ram_dat a(21) ad 4 alramadd17 n j5 abr_ram_ad( 15) n5 ch_ram_add (1) t29 vss y5 ch_ram_dat a(24) ad 5 vss j25 rx_dram_ad d(1) n11 vss u1 ch_ram_dat a(5) y25 se_d_in2(2) ad 25 vss j26 rx_dram_ad d(8) n13 vss u2 ch_ram_dat a(7) y26 se_d_in1(2) ad 26 tx_dram_da ta(26) j27 rx_dram_ad d(3) n15 vss u3 ch_ram_dat a(8) y27 se_d_in2(1) ad 27 tx_dram_da ta(28) j28 rx_dram_cl k n17 vss u4 ch_ram_dat a(12) y28 se_d_in3(0) ad 28 se_d_in0(0) j29 vss n19 vss u5 ch_ram_dat a(15) y29 vdd ad 29 se_d_in1(1) k1 vdd n25 rx_dram_ba u11 vss table 7. signal locations (continued) ball signal name ball signal name ball signal name ball signal name ball signal name
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 61 k2 ch_ram_add (8) n26 se_d_out3(2) u13 vss k3 ch_ram_clk n27 se_d_out2(3) u15 vss k4 abr_ram_cl k n28 se_d_out1(3) u17 vss k5 ch_ram_add 17n n29 se_d_out2(1) u19 vss table 7. signal locations (continued) ball signal name ball signal name ball signal name ball signal name ball signal name
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 62 ae1 vss af1 vss ag 1 vdd ah 1 vss aj1 vdd ae2 /alram_oe af2 /alram_we ag 2 alram_add(1 ) ah 2 vss aj2 vss ae3 alram_add(0 ) af3 alram_add(2 ) ag 3 alram_add(6 ) ah 3 vdd aj3 vdd ae4 alram_add(5 ) af4 alram_add(3 ) ag 4 alram_add(1 0) ah 4 alram_add(1 2) aj4 vss ae5 vdd af5 alram_add(7 ) ag 5 alram_add(1 1) ah 5 alram_add(1 5) aj5 vdd ae6 alram_add(8 ) af6 alram_add(1 3) ag 6 alram_add(1 6) ah 6 alram_data (0) aj6 alram_data (5) ae7 alram_add(9 ) af7 alram_add(1 4) ag 7 alram_add(1 7) ah 7 alram_data (1) aj7 vss ae8 alram_add(1 8) af8 alram_data (3) ag 8 alram_data (7) ah 8 alram_data (4) aj8 vss ae9 alram_data (2) af9 alram_data (8) ag 9 alram_data (14) ah 9 alram_data (15) aj9 vss ae1 0 alram_data (11) af1 0 alram_data (6) ag 10 alram_data (10) ah 10 alram_data (13) aj1 0 vdd ae1 1 alram_data (9) af1 1 alram_data (12) ag 11 alram_data (16) ah 11 tatm_clav(3 ) aj1 1 vdd ae1 2 tatm_soc af1 2 tatm_clav(0 ) ag 12 tatm_clav(1 ) ah 12 tatm_data(0 ) aj1 2 vss ae1 3 tatm_parity af1 3 tatm_data(1 ) ag 13 tatm_data(3 ) ah 13 tatm_data(5 ) aj1 3 tatm_data(6 ) ae1 4 / tatm_write_ en af1 4 tatm_clav(2 ) ag 14 tatm_data(2 ) ah 14 tatm_data(4 ) aj1 4 vdd ae1 5 tatm_data(9 ) af1 5 tatm_data(8 ) ag 15 tatm_data(7 ) ah 15 tatm_data(1 0) aj1 5 vss ae1 6 tatm_data(1 1) af1 6 tatm_data(1 3) ag 16 tatm_data(1 2) ah 16 tatm_data(1 4) aj1 6 vdd ae1 7 tx_dram_ad d(0) af1 7 tx_dram_ba ag 17 tatm_add(3) ah 17 tatm_data(1 5) aj1 7 tatm_add(1) ae1 8 tx_dram_ad d(1) af1 8 tatm_add(2) ag 18 tatm_add(0) ah 18 tx_dram_cl k aj1 8 vss ae1 9 / tx_dram_we af1 9 / tx_dram_ca s ag 19 / tx_dram_ra s ah 19 tatm_add(4) aj1 9 vdd ae2 0 tx_dram_da ta(0) af2 0 tx_dram_ad d(7) ag 20 tx_dram_ad d(3) ah 20 tx_dram_ad d(5) aj2 0 vdd table 7. signal locations (continued) ball signal name ball signal name ball signal name ball signal name ball signal name
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 63 4.3 signal descriptions (372 signal pins) all inputs and bidirectional inputs have internal pull up circuit except for /oe input. /oe has an internal pull down circuit. all 5v tolerant/ lvttl inputs have a schmitt trigger hysteresis circuit. all cmos inputs are not 5v tolerant. ae2 1 tx_dram_ad d(6) af2 1 tx_dram_da ta(2) ag 21 tx_dram_ad d(8) ah 21 tx_dram_dd( 2) aj2 1 vss ae2 2 tx_dram_da ta(4) af2 2 / tx_dram_cs( 0) ag 22 tx_dram_ad d(4) ah 22 tx_dram_da ta(3) aj2 2 vss ae2 3 tx_dram_da ta(18) af2 3 tx_dram_da ta(9) ag 23 tx_dram_da ta(5) ah 23 / tx_dram_cs( 1) aj2 3 vss ae2 4 tx_dram_da ta(11) af2 4 tx_dram_da ta(8) ag 24 tx_dram_da ta(6) ah 24 tx_dram_da ta(1) aj2 4 tx_dram_da ta(7) ae2 5 vdd af2 5 tx_dram_da ta(16) ag 25 tx_dram_da ta(14) ah 25 tx_dram_da ta(10) aj2 5 vss ae2 6 tx_dram_da ta(20) af2 6 tx_dram_da ta(17) ag 26 tx_dram_da ta(13) ah 26 tx_dram_da ta(12) aj2 6 vss ae2 7 tx_dram_da ta(25) af2 7 tx_dram_da ta(23) ag 27 tx_dram_da ta(19) ah 27 tx_dram_da ta(15) aj2 7 vdd ae2 8 tx_dram_da ta(29) af2 8 tx_dram_da ta(24) ag 28 tx_dram_da ta(21) ah 28 vss aj2 8 vss ae2 9 vss af2 9 vss ag 29 vss ah 29 vdd aj2 9 vdd table 7. signal locations (continued) ball signal name ball signal name ball signal name ball signal name ball signal name
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 64 4.3.1 processor interface signals 4.3.2 statistics interface signal table 8. processor interface signals (38 pins) signal name ball type drive/ input level slew rate description pclk c6 in cmos processor clock addrdata(31:0) b8, b7, d9, c8, d8, e10, c10, e9, d10, b10, c9, b9, c11, e12, e11, e13, d11, c12, d13, b11, b12, d12, c13, b13, c14, a13, b14, c15, d14, e14, b15, e15 bidir 5 ma/ 5 v or lv ttl mod- erate (mod) address/data bits 31 to 0 are part of the 32-bit processor address/data bus. /ads c7 in 5 v or lv ttl address/data status is an active low sig- nal that indicates an address state. w_/rd e8 in 5 v or lv ttl write_/read is an active high signal that selects a write cycle when it is high. /ready d7 out 5 ma mod ready is an active low signal that indi- cates the processor cycle is finished. when this signal is deasserted, it is driven high, then tristated. /cs a6 in 5 v or lv ttl chip select is an active low signal that selects the device for processor access. /intr b6 out 5 ma mod interrupt is an active low signal that indi- cates an interrupt is present. table 9. statistics interface signal (1 pin) signal name ball type drive/ input level slew rate description stats_strb d6 out 8 ma mod stats_strb is an active high signal that indicates a fixed position in the cell time in the sys_clk domain. this can be used to trigger external circuitry.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 65 4.3.3 switch element interface signals table 10. switch element interface signals (47 pins) signal name ball type drive/ input level slew rate description se_clk aa26 in cmos switch element clock is the 50 mhz or 66 mhz clock for nibble transfer. rx_cell_start w28 in 5 v or lv ttl receive cell start indicates the soc time in the receive direction. it should be driven high every cell time (118 se_clks). bp_ack_in(3:0) r27, u29, u28, t28 in 5 v or lv ttl backpressure input 3 down to 0. it carries the cell acknowledge and backpressure from the switch fabric. se_soc_out l27 out 8 ma mod switch fabric start of cell out indicates the soc for all four se_d_out signals. this sig- nal precedes the first nibble of cell by one clock. for cells leaving the qrt and entering the switch fabric, this signal indicates the soc. se_d_out0(3:0) p25, r28, r25, r26 out 5 ma mod switch element data out ports 3 down to 0 bits 3 down to 0 are four nibble-wide pathways that carry the cell to the qses (pm73488). se_d_out1(3:0) n28, p28, p26, p27 out 5 ma mod se_d_out2(3:0) n27, m26, n29, m27 out 5 ma mod se_d_out3(3:0) l26, n26, m28, l28 out 5 ma mod bp_ack_out(3:0) u27, t27, u26, v28 out 8 ma mod backpressure output 3 down to 0 asserts mul- tipriority backpressure and cell acknowledge toward the switch fabric. se_soc_in(3:0) v26, t25, v25, u25 in 5 v or lv ttl switch fabric start of cell 3 to 0 indicates the soc time in the transmit direction for the four incoming se_d_in3, se_d_in2, se_d_in1 and se_d_in0, respectively. se_d_in0(3:0) ab26, aa25, ac28, ad28 in 5 v or lv ttl switch element data in ports 3 to 0 bits 3 down to 0 are part of the nibble-wide, 50 mhz data pathway that carries the cell from the switch fabric. se_d_in1(3:0) ab27, y26, ad29, ab28 in 5 v or lv ttl se_d_in2(3:0) w26, y25, y27, w25 in 5 v or lv ttl se_d_in3(3:0) w27, aa28, aa27, y28 in 5 v or lv ttl
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 66 4.3.4 ch_ram interface signals table 11. ch_ ram interface signals (58 pins) signal name ball type drive/ input level slew rate description ch_ram_add(17:0) r5, r3, r4, n1, n2, n3, m2, n4, p3, k2, l2, p4, m4, m3, m5, p5, n5, h2 out 5 ma mod ch_ ram address bits 17 to 0 are part of the 18-bit sram address bus. ch_ram_data(31:0) ab5, ac3, ab2, ac2, aa4, ab3, ab4, y5, y3, aa5, y4, y2, aa3, aa2, w3, v5, u5, w4, v3, u4, w2, v2, v4, u3, u2, t2, u1, r2, t3, t4, t5, p2 bidir 5 ma/cmos mod ch_ram data bits 31 to 0 are part of the 32-bit sram data bus. ch_ram_parity0 w5 bidir 5 ma/cmos mod odd parity bit for ch_ram_data(15:0). ch_ram_parity1 ad3 bidir 5 ma/cmos mod odd parity bit for ch_ram_data(31:16). ch_ram_clk k3 out 8 ma fast ch_ram clock provides the clock to the ch_ram.this signal should be terminated with a series resistor before connecting to the ram mod- ules ch_ram_add17n k5 out 5 ma mod ch_ram not address bit 17 reverses bit 17 of ch_ram_add(17:0). /ch_ram_oe j2 out 8 ma fast ch_ram output enable is an active low signal that enables the sram to drive the ch_ram_data(31:0), ch_ram_parity0, and ch_ram_parity1.this signal should be terminated with a series resistor before connecting to the ram mod- ules /ch_ram_we0 j3 out 5 ma mod ch_ram write enable 0 is an active low signal that strobes ch_ram_data(15:0) and ch_ram_parity0 into an external sram. /ch_ram_we1 l3 out 5 ma mod ch_ram write enable 1 is an active low signal that strobes ch_ram_data(31:16) and ch_ram_parity1 into an external sram.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 67 4.3.5 al_ram interface signals /ch_ram_adsc l4 out 5 ma mod ch_ram synchronous address status controller is an active low signal that causes new addresses to be registered within the external ssram. table 12. address lookup ram interface signals (42 pins) signal name ball type drive/ input level slew rate description alram_add(18:0) ae8, ag7, ag6, ah5, af7, af6, ah4, ag5, ag4, ae7, ae6, af5, ag3, ae4, ac5, af4, af3, ag2, ae3 out 5 ma mod al ram address bits 18 to 0 are part of the 19-bit sram address bus. alram_data(16:0) ag11, ah9, ag9, ah10, af11, ae10, ag10, ae11, af9, ag8, af10, aj6, ah8, af8, ae9, ah7, ah6 bidir 5 ma/cmos mod al ram data bits 15 to 0 are part of the 16-bit sram data bus. bit 16 is for parity. alram_clk ad1 out 8 ma fast al ram clock provides the clock to the alram. this signal should be terminated with a series resistor before connecting to the ram modules alramadd17n ad4 out 5 ma mod al ram not address 17 reverses bit 17 of alram_add(18:0). alramadd18n ad2 out 5 ma mod al ram not address 18 reverses bit 18 of alram_add(18:0). /alram_oe ae2 out 8 ma fast al ram output enable is an active low signal that enables the sram to drive al_ram_data(16:0).this sig- nal should be terminated with a series resistor before connecting to the ram modules /alram_we af2 out 5 ma mod al ram write enable is an active low signal that strobes data into an external sram. /alram_adsc ac4 out 5 ma mod al ram synchronous address status controller is an active low signal that causes new addresses to be registered within the external ssram. table 11. ch_ ram interface signals (58 pins) (continued) signal name ball type drive/ input level slew rate description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 68 4.3.6 abr_ram interface signals table 13. abr_ram interface signals (22 pins) signal name ball type drive/ input level slew rate description abr_ram_ad(16:0) g2, j5, h4, f2, e2, g3, h5, f3, g4, d2, e3, f4, c2, f5, d3, g5, e4 bidir 5 ma/cmos mod abr ram address data bits 16 to 0 form the time division multiplexed address data bus. abr_ram_clk k4 out 8 ma fast abr ram clock provides the clock to the ab ram.this signal should be terminated with a series resistor before connecting to the ram modules /abr_ram_adsp j4 out 5 ma mod abr ram address data selection defines the type of information on the address/data bus (addrdata(31:0)). /abr_ram_oe l5 out 8 ma fast abr_ram output enable is an active low sig- nal that enables the ram to drive abr_ram_ad(16:0).this signal should be terminated with a series resistor before con- necting to the ram modules /abr_ram_adv h3 out 5 ma mod abr_ram advance is an active low signal that signals the external ssram to advance its address. /abr_ram_we f1 out 5 ma mod abr ram write enable is an active low signal that enables a write into the abr_ram.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 69 4.3.7 receive cell buffer drams note: dqm (i/o mask enables) pins to the sgram need to be tied to logic 0. table 14. receive cell buffer ram interface signals (49 pins) signal name ball type drive/ input level slew rate description rx_dram_add(8:0) j26, f28, k25, g28, h26, j27, k26, j25, k28 out 5 ma mod rx dram address bits 8 to 0 are part of the 9-bit sram address bus. note that tx_dram_add(8) must be connected to the autopre- charge pin.if dram_type = 1 (refer to rx_dram_type on page 104 ) then connect rx_dram_add(8) to the dram autoprecharge pin, which should be bit 10 of the dram address bus rx_dram_data(31:0) b23, e21, d22, b24, b25, c23, e22, c24, d23, b26, c25, d24, b27, e24, c26, e23, d25, c27, g25, b28, e26, c28, e27, d27, d28, f25, e28, g26, f26, f29, f27, g27 bidir 5 ma/cmos mod receive dram data bits 31 to 0 are part of the 32-bit sram data bus. rx_dram_clk j28 out 8 ma fast receive dram clock provides the clock to the sdram.this signal should be terminated with a series resistor before connecting to the ram modules dram_cke l25 out 5 ma mod dram clock enable provides a clock enable signal for rx_dram and tx_dram /rx_dram_cs(1:0) h25, h28 out 5 ma mod receive dram chip select bits 1 to 0 enable the sdrams. if dram_type = 1 (refer to rx_dram_type on page 104 ), these are rx_dram_add(9:8). rx_dram_ba n25 out 5 ma mod receive dram bank address defines the bank to which the opera- tion is addressed. /rx_dram_ras k27 out 5 ma mod receive dram row address strobe is an active low signal that writes in the row address. /rx_dram_cas m25 out 5 ma mod receive dram column address strobe is an active low signal that writes in the column address. /rx_dram_we h27 out 5 ma mod receive dram write enable is an active low signal that enables a write into the synchronous dram.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 70 4.3.8 transmit cell buffer drams table 15. transmit cell buffers ram interface signals (48 pins) signal name ball type drive/ input level slew rate description tx_dram_add(8:0) ag21, af20, ae21, ah20, ag22, ag20, ah21, ae18, ae17 out 5 ma mod transmit dram address bits 8 to 0 are part of the 9-bit dram address bus. note that tx_dram_add(8) must be connected to the autoprecharge pin. if dram_type = 1 (refer to rx_dram_type on page 104 ) then connect tx_dram_add(8) to the dram autoprecharge pin, which should be bit 10 of the dram address bus. tx_dram_data(31:0) ab25, ac27, ae28, ad27, ac26, ad26, ae27, af28, af27, ac25, ag28, ae26, ag27, ae23, af26, af25, ah27, ag25, ag26, ah26, ae24, ah25, af23, af24, aj24, ag24, ag23, ae22, ah22, af21, ah24, ae20 bidir 5 ma/cmos mod transmit dram data bits 31 to 0 are part of the 32-bit dram data bus. tx_dram_clk ah18 out 8 ma fast transmit dram clock pro- vides the clock to the sdram.this signal should be terminated with a series resistor before connecting to the ram modules /tx_dram_cs(1:0) ah23, af22 out 5 ma mod transmit dram chip select bits 1 and 0 select the sdram devices. if dram_type = 1 (refer to rx_dram_type on page 104 ), then these are tx_dram_add(9:8). tx_dram_ba af17 out 5 ma mod transmit dram bank address defines the bank to which the operation is addressed. /tx_dram_ras ag19 out 5 ma mod transmit dram row address strobe is an active low signal that writes in the row address. /tx_dram_cas af19 out 5 ma mod transmit dram column address strobe is an active low signal that writes in the column address.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 71 note: dqm (i/o mask enables) pins to the sgram or sdram need to be tied to logic 0. /tx_dram_we ae19 out 5 ma mod transmit dram write enable is an active low signal that enables a write into the syn- chronous dram. table 15. transmit cell buffers ram interface signals (48 pins) (continued) signal name ball type drive/ input level slew rate description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 72 4.3.9 utopia atm layer interface signals 4.3.9.1 transmit utopia atm layer interface signals 4.3.9.2 receive utopia atm layer interface signals table 16. transmit utopia atm layer interface signals (29 pins) signal name ball type drive/input level slew rate description atm_clk v27 in cmos utopia atm layer clock provides timing information for both the transmit and receive utopia interfaces. tatm_add(4:0) ah19, ag17, af18, aj17, ag18 out 12 ma mod transmit utopia atm layer address bits 4 to 0 . tatm_data(15:0) ah17, ah16, af16, ag16, ae16, ah15, ae15, af15, ag15, aj13, ah13, ah14, ag13, ag14, af13, ah12 out 12 ma mod transmit utopia atm layer data bits 15 to 0 are part of the 16-bit uto- pia transmit data bus that carries data toward the phy layer device. tatm_clav(3:0) ah11, af14, ag12, af12 in 5 v or lv ttl transmit utopia atm layer cell available bits 3 to 0 are active high sig- nals that indicate the selected phy layer devices may accept another cell. tatm_soc ae12 out 12 ma mod transmit utopia atm layer start- of-cell marks the start of a cell. /tatm_write_en ae14 out 12 ma mod transmit utopia atm layer write enable enables the write of a cell byte. tatm_parity ae13 out 12 ma mod transmit utopia atm layer odd parity bit over tatm_data(15:0). table 17. receive utopia atm layer interface signals (27 pins) signal name ball type drive/ input level slew rate description ratm_add(4:0) c19, c21, b21, e20, d19 out 12 ma mod receive utopia atm layer address bits 4 to 0 ratm_data(15:0) d15, a17, b17, c17, b18, d17, c16, b20, b19, d16, d18, c18, e18, e16, e17, b22 in 5v or lv ttl receive utopia atm layer data bits 15 to 0 are part of the 16-bit utopia receive data bus that carries data from the phy layer device. ratm_soc d21 in 5v or lv ttl receive utopia atm layer start-of- cell marks the start of a cell. ratm_clav(3:0) c22, e19, a24, d20 in 5v or lv ttl receive utopia atm layer cell available bits 0 to 3 indicate the selected phy layer devices have another cell. /ratm_read_en c20 out 12 ma mod receive utopia atm layer read enable causes a read from the fifo in the phy layer device.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 73 4.3.10 boundary scan signals table 18. test signals (8 signal pins) signal name ball type drive/input level slew rate description /jtag_reset c4 in cmos jtag reset is an active low, true asynchronous reset to the jtag controller. jtag_tck b5 in cmos scan test clock is an independent clock used to drive the inter- nal boundary scan test logic. connect this signal to vdd through a pull-up resistor. jtag_tdi b4 in cmos scan test data input is the serial input for boundary scan test data and instruction bits. connect this signal to vdd through a pull-up resistor. jtag_tdo b3 out 4 ma mod scan test data output is the serial output for boundary scan test data. jtag_tms c5 in cmos scan test mode select controls the operation of the boundary scan test logic. connect this signal to vdd through a pull-up resistor. /test_mode d4 in cmos this is a manufacturing test mode bit for manufacturing test. it must be pulled up for functional mode on the board. /scan_en e7 in cmos scan test enable is used to enable the internal scan test logic. connect this signal to vdd through a pull-up resistor. proc_mon t26 out n/a n/a process monitor is used for manufacturing test. it is connected to a nand tree that may be used for vil/vih testing.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 74 4.3.11 miscellaneous signals table 19. miscellaneous signals (3 signal pins) signal name ball type drive /input level slew description sysclk b16 in cmos system clock provides a high speed clock input for the state machine and the mem- ory interfaces. /oe d5 in cmos output enable is an active low signal that enables all the outputs of the device. set- ting it high will tri-state all outputs except procmon and disable all input pull up resistors for in-circuit idd tests. /reset c3 in 5v or lv ttl reset is an active low signal used to ini- tialize or re-initialize the device. se_clk must be present for the reset to take effect. vdd a3, a5, a10, a11, a14, a16, a19, a20, a27, a29, b2, c1, c29, k1, k29, l1, l29, p1, p29, t1, v29, w1, w29, y1, y29, ac29, ae5, ag1, ah3, ah29, aj1, aj3, aj5, aj10, aj11, aj14, aj16, aj19, aj20, aj27, aj29, e5, e25, ae25 in n/a supply voltage 3.3 5% v. vss a2, a4, a7, a8, a9, a12, a15, a18, a21, a22, a23, a25, a26, a28, b1, b29, d1, d26, d29, e1, e6, e29, g1, g29, h1, h29, j1, j29, l11, l13, l15, l17, l19, m1, m29, n11, n13, n15, n17, n19, r1, r11, r13, r17, r19, r29, t29, u11, u13, u15, u17, u19, v1, w11, w13, w15, w17, w19, aa1, aa29, ab1, ab29, ac1, ad5, ad25, ae1, ae29, af1, af29, ag29, ah1, ah2, ah28, aj2, aj4, aj7, aj8, aj9, aj12, aj15, aj18, aj21, aj22, aj23, aj25, aj26, aj28 in n/a ground.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 75 5 physical characteristics . . symbol parameter conditions min max unit v dd supply voltage with respect to gnd -0.3 3.9 v i out dc output current, per pin -12 12 ma t stg storage temperature -65 125 c t r input rise time 10 ns t f input fall time 10 ns symbol parameter conditions min max unit v dd supply voltage 3.14 3.46 v v o output voltage 0 v dd v t a operating temperature -40 85 c symbol parameter conditions min typ max unit v iht high-level ttl input voltage all 5v tolerant /lvttl inputs 2.15 v dd 5.5v v v ihc high-level cmos input volt- age all cmos inputs 2.0 v dd v dd + 0.3 v v il low-level input voltage all 5v tolerant /lvttl and cmos inputs v ss - 0.3 00.8v v oh cmos high-level output volt- age i oh = - specified dc drive current (in pin description section) assuming the utopia interface drivers are not simul- taneously loaded at 12 ma 2.4 v dd v v ol cmos low-level output volt- age i ol = specified dc drive current(in pin description section) assuming the utopia interface drivers are not simultaneously loaded at 12 ma 0.4 v i typ typical operating current, out- put unloaded se_clk = 50 mhz sys_clk= 100 mhz atm_clk = 66 mhz 600 900 ma notes: v cc = 3.3v 10%, t a = -40c to 85c for industrial use. typical values are t a = 25c and v cc = 3.3 v.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 76 note: ? the junction temperature must be kept below 125c while the device is operating. symbol parameter conditions min max unit c in input capacitance 6 pf c out output capacitance 6 pf c load load capacitance to meet timing on any signal. 30 pf notes: capacitance measured at 25 c. sample tested only. table 20. estimated package thermal characteristics symbol parameter condition typical unit q jc junction to case thermal resistance 3.3 c/watt q ja junction to ambient thermal resistance still air 14.9 c/watt q ja junction to ambient thermal resistance 200 lfpm 12.6 c/watt q ja junction to ambient thermal resistance 400 lfpm 11.8 c/watt q ja junction to ambient thermal resistance 600 lfpm 11.2 c/watt
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 77 6 timing diagrams all pin names are described in section 4 pin descriptions starting on page 55 . unless otherwise indicated, all output timing delays assume a capacitive loading of 30 pf 6.1 utopia timing figure 50 shows the receive utopia 50 mhz timing (the ratm_add and ratm_clav val- ues are shown in hexadecimal). figure 50. receive utopia 50 mhz timing symbol parameter signals min max unit atm_clk frequency atm_clk 55 mhz atm_clk duty cycle atm_clk 40 60 % traddq clock-to-output valid time ratm_add(4:0) 3.4 10.5 ns trclavsu input setup time ratm_clav(3:0) 4 ns trclavh input hold time ratm_clav(3:0) 1 ns trenq clock-to-output valid time /ratm_read_en 3.5 9.5 ns trsocsu input setup time ratm_soc 4 ns trdatasu input setup time ratm_data(15:0) 4 ns trdath input hold time ratm_data(15:0) 1 ns 1 2 3 4 5 6 7 8 9 10 11 12 trdatasu trdath traddq trenq trclavsu trclavh trsocsu hh p hpppp 01 1f 1f 1f 00 01 101010 p atm_clk ratm_data(15:0) ratm_add(4:0) /ratm_read_en ratm_clav(3:0) ratm_soc
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 78 figure 51 shows the transmit utopia 50 mhz timing. figure 51. transmit utopia 50 mhz timing symbol parameter signals min max unit atm_clk frequency atm_clk 55 mhz ttaddq clock-to-output valid time tatm_add(4:0) 3.4 12 ns ttclavsu input setup time tatm_clav(3:0) 2 ns ttwenq clock-to-output valid time /tatm_write_en 3.3 9.5 ns ttsocq clock-to-output valid time tatm_soc 3.3 9.5 ns ttdataq clock-to-output valid time tatm_data(15:0) 3.3 12 ns ttclavh input hold time tatm_clav(3:0) 2 ns ttparq clock-to-output valid time tatm_parity 3.8 11 ns 1 2 3 4 5 6 7 8 9 ttdataq ttaddq ttwenq ttclavsu ttclavh ttsocq ttparq hp p pp 04 1f 1f 1f 00 01 1f 02 03 010101 hh p 00 atm_clk tatm_data(15:0) tatm_add(4:0) /tatm_write_en tatm_clav(3:0) tatm_soc tatm_parity
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 79 6.2 dram external memory timing note: all inputs are the minimum required. all outputs are the minimum expected. all inputs and outputs are assume to have a 30 pf capacitive loading. the rx_dram_clk and tx_dram_clk are assume to have a 22 ohm series terminated resister connected to a combined capacitive load of 36 pf. figure 52 shows the receive dram external memory 100 mhz read timing. figure 52. receive dram external memory 100 mhz read timing symbol parameter signals min max unit tcyc clock period rx_dram_clk 10 ns tch clock high period rx_dram_clk 3 ns tcl clock low period rx_dram_clk 3 ns taddrsu address setup time rx_dram_add(8:0) 2.7 ns tbasu bank address setup time rx_dram_ba 2.9 ns taddrh address hold time rx_dram_add(8:0) 1.3 ns tbah bank address hold time rx_dram_ba 1.5 ns tckh enable hold time * dram_cke ns tcksu enable setup time * dram_cke ns trassu ras setup time /rx_dram_ras 3.1 ns trash ras hold time /rx_dram_ras 1.5 ns tcassu cas setup time /rx_dram_cas 3.2 ns tcash cas hold time /rx_dram_cas 1.5 ns tcssu chip select setup time /rx_dram_cs(1:0) 2.4 ns tcsh chip select hold time /rx_dram_cs(1:0) 2.2 ns trdh required hold time required (read data) rx_dram_data(31:0) 2.7 ns tcyc tcyc tch tcl tch tcl tcksu tckh tcssu tcsh trassu trash tcassu tcash taddrsu taddrh twesu tweh trds trdh tbasu tbah row column valid data rx_dram_clk dram_cke /rx_dram_cs(1:0) /rx_dram_ras /rx_dram_cas rx_dram_add(8:0) /rx_dram_we rx_dram_data(31:0) rx_dram_ba
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 80 figure 53 shows the receive dram external memory 100 mhz write timing. twesu write enable setup time /rx_dram_we 2.8 ns tweh write enable hold time /rx_dram_we 1.5 ns trds required setup time (read data) rx_dram_data(31:0) 0 ns figure 53. receive dram external memory 100 mhz write timing symbol parameter signals min max unit tcyc clock period rx_dram_clk 10 ns tch clock high period rx_dram_clk 3 ns tcl clock low period rx_dram_clk 3 ns taddrsu address setup time rx_dram_add(8:0) 2.7 ns taddrh address hold time rx_dram_add(8:0) 1.3 ns tbasu bank address setup time rx_dram_ba 2.9 ns tbah bank address hold time rx_dram_ba 1.5 ns tckh clock enable hold time * dram_cke * ns tcksu clock enable setup time * dram_cke * ns trassu ras setup time /rx_dram_ras 3.1 ns trash ras hold time /rx_dram_ras 1.5 ns tcassu cas setup time /rx_dram_cas 3.2 ns tcash cas hold time /rx_dram_cas 1.5 ns tcssu chip select setup time /rx_dram_cs(1:0) 2.4 ns tcsh chip select hold time /rx_dram_cs(1:0) 2.2 ns symbol parameter signals min max unit 12 34 56 78 tcyc tcyc tch tcl tch tcl tcksu tckh tcssu tcsh trassu trash tcassu tcash taddrsu taddrh twesu tweh tdsu tdh tbasu tbah row column valid data valid data valid data rx_dram_clk dram_cke /rx_dram_cs(1:0) /rx_dram_ras /rx_dram_cas rx_dram_add(8:0) /rx_dram_we rx_dram_data(31:0) rx_dram_ba
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 81 * the dram_cke is a functionally static signal. software should ensure that the dram_cke is set at least 1 microsecond before desserting the sw_reset bit. figure 54 shows the transmit dram external memory 100 mhz read timing. twesu write enable setup time /rx_dram_we 2.8 ns tweh write enable setup time /rx_dram_we 1.5 ns tdsu (write) data valid before clock rx_dram_data(31:0) 2.4 ns tdh (write) data valid after clock rx_dram_data(31:0) 1 ns figure 54. transmit dram external memory 100 mhz read timing symbol parameter signals min max unit tcyc clock period tx_dram_clk 10 ns tch clock high period tx_dram_clk 3 ns tcl clock low period tx_dram_clk 3 ns taddrsu address setup time tx_dram_add(8:0) 3.1 ns taddrh address hold time tx_dram_add(8:0) 1.3 ns tbasu bank address setup time tx_dram_ba 2.8 ns tbah bank address hold time tx_dram_ba 1.5 ns tckh clock enable hold time dram_cke * ns symbol parameter signals min max unit 1 2 3 4 5 6 7 8 tcyc tcyc tch tcl tch tcl tcksu tckh tcssu tcsh trassu trash tcassu tcash taddrsu taddrh twesu tweh trds trdh tbasu tbah row column valid data tx dram read cycle tx_dram_clk dram_cke /tx_dram_cs(1:0) /tx_dram_ras /tx_dram_cas tx_dram_add(8:0) /tx_dram_we tx_dram_data(31:0) tx_dram_ba
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 82 figure 55 shows the transmit dram external memory 100 mhz write timing. tcksu clock enable setup time dram_cke * ns trassu ras setup time /tx_dram_ras 3.3 ns trash ras hold time /tx_dram_ras 1.5 ns tcassu cas setup time /tx_dram_cas 3.3 ns tcash cas hold time /tx_dram_cas 1.5 ns tcssu chip select setup time /tx_dram_cs(1:0) 2.7 ns tcsh chips select hold time /tx_dram_cs(1:0) 1.5 ns trdh (read) data valid required after clock tx_dram_data(31:0) 2 ns twesu write enable setup time /tx_dram_we 2.9 ns tweh write enable hold time /tx_dram_we 1.5 ns trds (read) data valid required before clock tx_dram_data(31:0) 0 ns figure 55. transmit dram external memory 100 mhz write timing symbol parameter signals min max unit tcyc tx_dram_clk period tx_dram_clk 10 ns tch tx_dram_clk high period tx_dram_clk 3 ns tcl tx_dram_clk low period tx_dram_clk 3 ns taddrsu address setup time tx_dram_add(8:0) 3.1 ns taddrh address hold time tx_dram_add(8:0) 1.3 ns tbasu bank address setup time tx_dram_ba 2.8 ns tbah bank address hold time tx_dram_ba 1.5 ns symbol parameter signals min max unit 12 34 56 78 tcyc tcyc tch tcl tch tcl tcksu tckh tcssu tcsh trassu trash tcassu tcash taddrsu taddrh twesu tweh tdsu tdh tbasu tbah row column valid data valid data valid data valid data tx_dram_clk dram_cke /tx_dram_cs(1:0) /tx_dram_ras /tx_dram_cas tx_dram_add(8:0) /tx_dram_we tx_dram_data(31:0) tx_dram_ba
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 83 * the dram_cke is a functionally static signal. software should ensure that the dram_cke is set at least 1 microsecond before desserting the sw_reset bit. 6.3 sram timings all inputs and outputs are assume to have a 30 pf capacitive loading. the alram_clk, abram_clk and chram_clk are assume to have a 22 ohm series terminated resister connected to a combined capacitive load of 36 pf. figure 56 shows the al ram read timing. tckh clk enable hold time dram_cke * ns tcksu clk enable setup time dram_cke * ns trassu ras setup time /tx_dram_ras 3.3 ns trash ras hold time /tx_dram_ras 1.5 ns tcassu cas setup time /tx_dram_cas 3.3 ns tcash cas hold time /tx_dram_cas 1.5 ns tcssu chip select setup time /tx_dram_cs(1:0) 2.7 ns tcsh chip select hold time /tx_dram_cs(1:0) 1.5 ns twesu write enable setup time /tx_dram_we 2.9 ns tweh write enable hold time /tx_dram_we 1.5 ns tdsu (write) data valid before clock tx_dram_data(31:0) 2.2 ns tdh (write) data valid after clock tx_dram_data(31:0) 1.5 ns figure 56. address lookup ram read timing symbol parameter signals min max unit 1 2 3 4 5 tcyc tcyc tch tcl tch tcl tadss tadh toesu toeh tadrsu tadrh tadrsu tadh tadrsu tadrh twesu tweh trds trdh valid data alram read cycle alram_clk /alram_adsc /alram_oe alram_add(18:0) alramadd17n alramadd18n /alram_we alram_data(16:0)
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 84 figure 57 shows the al ram write timing. symbol parameter signals min max units tcyc clock period alram_clk 10 ns tch clock high period alram_clk 3 ns tcl clock low period alram_clk 3 ns tadrsu address setup time alram_add(18:0), alramadd17n, alramadd18n 2.7 ns tadrh address hold time alram_add(18:0), alramadd17n, alramadd18n 1.5 ns toesu output enable setup time /alram_oe 3.5 ns toeh output enable hold time /alram_oe -1 ns tadss address strobe setup time /alram_adsc 2.8 ns tadh address strobe hold time /alram_adsc 1.5 ns trds (read) data valid required before clock alram_data(16:0) 3.8 ns trdh (read) data valid required after clock alram_data(16:0) 1.5 ns twesu write enable setup time /alram_we 2.9 ns tweh write enable hold time /alram_we 1.2 ns figure 57. address lookup ram write timing 1 2 3 4 5 tcyc tcyc tch tcl tch tcl tadss tadh toesu toeh tadrsu tadrh tadrsu tadrh tadrsu tadrh twesu tweh tds tdh valid data alram write cycle alram_clk alram_adsc /alram_oe alram_add(18:0) alramadd17n alramadd18n alram_we alram_data(16:0)
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 85 figure 58 shows the channel ram read timing. symbol parameter signals min max units tcyc clock period alram_clk 10 ns tch clock high period alram_clk 3 ns tcl clock low period alram_clk 3 ns tadrsu address setup time alram_add(18:0), alramadd17n, alramadd18n 2.7 ns tadrh address hold time alram_add(18:0), alramadd17n, alramadd18n 1.5 ns toesu output enable setup time /alram_oe 3.5 ns toeh output enable hold time /alram_oe -1 ns tadss address strobe setup time /alram_adsc 2.8 ns tadh address strobe hold time /alram_adsc 1.5 ns tds (write) data valid before clock alram_data(16:0) 2.6 ns tdh (write) data valid after clock alram_data(16:0) 1.5 ns twesu write enable setup time /alram_we 2.9 ns tweh write enable hold time /alram_we 1.2 ns figure 58. channel ram read timing 1 2 3 4 5 tcyc tcyc tch tcl tch tcl tadss tadh toesu toeh tas tah tas tah twesu tweh trds trdh trds trdh trds trdh valid data chram read cycle ch_ram_clk /ch_ram_adsc /ch_ram_oe ch_ram_add(17:0) ch_ram_add17n /ch_ram_we ch_ram_data(31:0) ch_ram_parity0 ch_ram_parity1
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 86 figure 59 shows the channel ram write timing. symbol parameter signals min max units tcyc clock period ch_ram_clk 10 ns tch clock high period ch_ram_clk 3 ns tcl clock low period ch_ram_clk 3 ns tas address setup time ch_ram_add(17:0), ch_ram_add17n 3.1 ns tah address hold time ch_ram_add(17:0), ch_ram_add17n 1ns toesu output enable setup time /ch_ram_oe 3.5 ns toeh output enable hold time /ch_ram_oe -1 ns tadss address strobe setup time /ch_ram_adsc 3.2 ns tadh address strobe hold time /ch_ram_adsc 1 ns trds (read) data valid required before clock ch_ram_data(31:0) 4.7 ns trdh (read) data valid required after clock ch_ram_data(31:0) 1 ns twesu write enable setup time /ch_ram_we 3.3 ns tweh write enable hold time /ch_ram_we 1 ns figure 59. channel ram write timing 1 2 3 4 5 tcyc tcyc tch tcl tch tcl tadss tadh toesu toeh tas tah tas tah twesu tweh tds tdh tds tdh tds tdh valid data chram write cycle ch_ram_clk /ch_ram_adsc /ch_ram_oe ch_ram_add(17:0) ch_ram_add17n /ch_ram_we ch_ram_data(31:0) ch_ram_parity0 ch_ram_parity1
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 87 figure 60 shows the ab ram read timing. symbol parameter signals min max units tcyc clock period ch_ram_clk 10 ns tch clock high period ch_ram_clk 3 ns tcl clock low period ch_ram_clk 3 ns tas address setup time ch_ram_add(17:0), ch_ram_add17n 3.1 ns tah address hold time ch_ram_add(17:0), ch_ram_add17n 0.8 ns toesu output enable setup time /ch_ram_oe 3.5 ns toeh output enable hold time /ch_ram_oe -1 ns tadss address strobe setup time /ch_ram_adsc 3.2 ns tadh address strobe hold time /ch_ram_adsc 1 ns tds (write) data valid before clock ch_ram_data 2.5 ns tdh (write) data valid after clock ch_ram_data 1 ns twesu write enable setup time /ch_ram_we 3.3 ns tweh write enable hold time /ch_ram_we 1 ns figure 60. ab ram read timing 1 2 3 4 5 tcyc tcyc tch tcl tch tcl tadspsu tadsph toesu toeh tadrsu tadrh trds trdh twesu tweh tadvnsu tadvnh abram read cycle address data 1 data 2 abr_ram_clk /abr_ram_adsp /abr_ram_oe abr_ram_ad(16:0) /abr_ram_we /abr_ram_adv
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 88 figure 61 shows the ab ram write timing. symbol parameter signals min max units tcyc clock period ab_ram_clk 10 ns tch clock high period ab_ram_clk 3 ns tcl clock low period ab_ram_clk 3 ns tadrsu (read) required data valid before clock adress setup time ab_ram_ad(16:0) 2.6 ns tadrh (read) required data valid after clock address hold time ab_ram_ad(16:0) 1 ns trds (read) required data valid before clock ab_ram_ad(16:0) 3.5 trdh (read) required data valid after clock ab_ram_ad(16:0) 1 twesu write enable setup time /ab_ram_we 3.5 ns tweh write enable hold time /ab_ram_we 1 ns tadspsu address status processor setup time /ab_ram_adsp 3.3 ns tadsph address status processor hold time /ab_ram_adsp 1 ns tadvnsu address advance setup time /ab_ram_adv 3.4 ns tadvnh address advance hold time /ab_ram_adv 1 ns toesu output enable setup time /ab_ram_oe 1.4 ns toeh output enable hold time /ab_ram_oe -1 ns figure 61. ab ram write timing 1 2 3 4 5 tch tcl tcyc tcyc tch tcl tadspsu tadsph tadrsu tadrh tadrsu tadrh twesu tweh address data 1 abram write cycle abr_ram_clk /abr_ram_adsp /abr_ram_oe abr_ram_ad(16:0) /abr_ram_we /abr_ram_adv
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 89 symbol parameter signals min max units tcyc clock period ab_ram_clk 10 ns tch clock high period ab_ram_clk 3 ns tcl clock low period ab_ram_clk 3 ns tadrsu (write) required data valid before clock adress setup time ab_ram_ad(16:0) 2.6 ns tadrh (write) required data valid after clock address hold time ab_ram_ad(16:0) 1 ns twesu write enable setup time /ab_ram_we 3.5 ns tweh write enable hold time /ab_ram_we 1 ns tadspsu address status processor setup time /ab_ram_adsp 3.3 ns tadsph address status processor hold time /ab_ram_adsp 1 ns
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 90 6.4 qrt-qse interface timing output timing delays assume a capacitive loading of 30 pf on se_d_out(3:0,3:0) and 48 pf on se_soc_out. figure 62 shows the bit-level timing for the qrt.. figure 62. qrt bit-level timing symbol parameter signals min max unit fseclk** frequency of se_clk se_clk 65.4 68 mhz clock duty cycle se_clk 40 60 % <10 khz jitter tolerance * bp_ack_in(3:0), se_soc_in(3:0) 2 clock period >10 khz jitter tolerance * bp_ack_in(3:0), se_soc_in(3:0) 0.35 clock period tctsu control signal setup time rx_cell_start 1.5 ns tctho control signal hold time rx_cell_start 0 ns tsesu* setup time before se_clk se_d_in(3:0,3:0), se_soc_in(3:0), bp_ack_in(3:0) 4.0 ns tseho* hold time after se_clk se_d_in(3:0,3:0), se_soc_in(3:0), bp_ack_in(3:0) 1.5 ns tseq output delay from se_clk se_d_out(3:0,3:0), bp_ack_out(3:0), se_soc_out 2.9 10.0 ns output delay skew * se_d_out(0,3:0) and se_soc_out se_d_out(1,3:0) and se_soc_out se_d_out(2,3:0) and se_soc_out se_d_out(3,3:0) and se_soc_out 1.3 ns input delay skew * se_d_in(0,3:0) and se_soc_in(0) se_d_in(1,3:0) and se_soc_in(1) se_d_in(2,3:0) and se_soc_in(2) se_d_in(3,3:0) and se_soc_in(3) 3ns tctsu tsesu fseclk fseclk tseho tseq tctho tseq se_clk se_d_in(3:0,3:0), bp_ack_in(3:0) se_d_out(3:0,3:0), bp_ack_out(3:0) rx_cell_start se_soc_out
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 91 6.4.1 switch fabric cell formats table 21 on page 91 and table 22 on page 92 define the switch fabric interface cell formats for data cells and idle cells, respectively. table 21. qrt-qse interface cell format. * when the phase aligners are turned on, tsesu and tseho are no longer defined. however, the maximum input and output skew and jitter on these signals with respect to the se_soc_in is constrained to specification listed in this table. ** this is assuming the sysclk is operating at 100 mhz. to operate the device fabric interface at other frequencies, refer to relationships among various clock domains on page 229 . nibble symbol definition comment 0 pres(1:0), mc, sp pres = 10 b : valid cell present. pres = 01 b : idle cell. pres = 00 b : invalid cell. pres = 11 b : invalid cell. mc = 1 b : multicast cell. sp: spare bit. programmed via the rx_ch_config register (refer to section 9.3.1.1 rx_ch_config starting on page 184 ). 1sp(1:0), prior- ity(1:0) sp(1:0) spare bits. priority = 11 b high-priority cell. 10 b medium-priority cell. 01 b low-priority cell. 00 b undefined. cell discarded by qse. the qrt should be configured never to gen- erate priority 00 b cells, since they are dis- carded by the qse. 2 tag_0_6 routing tag 0. mcg_3 the qse interprets all four nib- bles as the mcg. 3 tag_1_7 routing tag 1. mcg_2 4 tag_2 routing tag 2. mcg_1 5 tag_3 routing tag 3. mcg_0 6 tag_4 routing tag 4. 7 tag_5 routing tag 5. 8 tag_0_6 routing tag 6. 9 tag_1_7 routing tag 7. 10 outchan_3 intepreted as outchan(15:12) by the qrt. not used by the qse. symbol parameter signals min max unit
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 92 table 22. qrt-qse interface idle cell format 11 sp(1:0), mb, p sp(1:0) spare bits. mb mark bit. cells that are present and have this bit set are counted by the tx_marked_cells and rx_marked_cells counters (refer to marked_cells_count on page 110 ). p set to odd parity by software over nibbles 0-11. 12 outchan_2 intepreted as outchan(11:8) by the qrt. not used by the qse. 13 outchan_1 intepreted as outchan(7:4) by the qrt. not used by the qse. 14 outchan_0 intepreted as outchan(3:0) by the qrt. not used by the qse. 15 vci_3 intepreted as vci(15:12) by the qrt. not used by the qse. 16 vci_2 intepreted as vci(11:8) by the qrt. not used by the qse. 17 vci_1 intepreted as vci(7:4) by the qrt. not used by the qse. 18 vci_0 intepreted as vci(3:0) by the qrt. not used by the qse. 19 pti(2:0)/clp intepreted as the pti and clp field from the cell by the qrt. not used by the qse. 20 seq_1 intepreted as seq(7:4) by the qrt. not used by the qse. 21 seq_0 intepreted as seq(3:0) by the qrt. not used by the qse. 22-117 payload interpreted as 48 bytes of atm cell payload by the qrt. not used by the qse. nibble symbol definition comment 0 pres(3:0) pres = 0100 b : cell not present. 1 idle_0 idle_0 = 0000 b : all 0. 2 idle_1 idle_1 = 1000 b : marching 1. marching 1 pattern protects against bridging faults. if the qrt is not in sync with rx_cell_start, the device outputs 1010 b here. 3 idle_2 idle_2 = 0100 b : marching 1. marching 1 pattern protects against bridging faults. 4 idle_3 idle_3 = 0010 b : marching 1. 5 idle_4 idle_4 = 0001 b : marching 1. 6 idle_5 idle_5 = 000 b . 7 idle_6 idle_6 = 000 b . 8 - 15 reserved the qrt currently outputs 000 b . 16-117 unused the qrt currently outputs 000 b . nibble symbol definition comment
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 93 6.5 processor interface timing a microprocessor cycle starts when the chip select (/cs) and command (/ads) are asserted. dur- ing read cycles, the device asserts /ready to indicate that data on the data bus is valid and dur- ing write cycles the chip asserts /ready to indicate that the write has finished and data from the bus can be removed. the microprocessor can terminate the current cycle at any time. as shown in figure 63, the device stops driving the bus and deasserts all control lines when the cycle termi- nates. the current cycle terminates when the device select is deasserted or both read and write are deasserted. a new cycle can start once the /ready has been deasserted. if the cycle was termi- nated prematurely before the /ready was asserted, then a new microprocessor cycle can start after one clock cycle. figure 63. microprocessor read timing symbol parameter signals min max unit tcyc processor clock frequency pclk 12.5 50 mhz taddrsu input address setup time addrdata(31:0) 3 ns taddrh input address hold time addrdata(31:0) 1 ns tradsu address strobe setup time /ads 3 ns tradsh address strobe hold time /ads 1 ns tcssu chip select setup time /cs 3 ns tcsh chip select hold time /cs 1 ns ...... ...... ...... ...... ...... ...... ...... ...... tcyc tcyc tcssu tcsh tradsu tradsh taddrsu taddrh tdath twesu tweh trclkq trclkq addr microprocessor read cycle data pclk /cs /ads addrdata(31:0) w_/rd /intr /ready
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 94 twesu write enable setup w_/rd 1 ns tweh write enable hold time w_/rd 1 ns tdath data hold time addrdata(31:0) 2 ns trclkq acknowledge to output valid /ready 2 9 ns figure 64. microprocessor write timing symbol parameter signals min max unit tcyc processor clock frequency pclk 12.5 50 mhz clock duty cycle pclk 40 60 % taddrsu input address setup time addrdata(31:0) 3 ns taddrh input address hold time addrdata(31:0) 1 ns tradsu address strobe setup time /ads 3 ns tradsh address strobe hold time /ads 1 ns tcssu chip select setup time /cs 3 ns tcsh chip select hold time /cs 1 ns tclkq acknowledge to output valid /ready 2 9 ns tdath data hold time addrdata(31:0) 1 ns symbol parameter signals min max unit ...... ...... ...... ...... ...... ...... ...... ...... tcyc tcyc tcssu tcsh tradsu tradsh taddrsu taddrh tdatsu tdath tclkq tclkq addr microprocessor write cycle data pclk /cs /ads addrdata(31:0) w_/rd /intr /ready
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 95 tdatsu data setup time addrdata(31:0) 3 ns symbol parameter signals min max unit
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 96 6.6 miscellaneous timing figure 65 shows the reset pin (/reset) timing. the /reset signal must be asserted for a mini- mum time (tres) to be registered properly in the presence of se_clk. the qrt remains in reset while /reset is asserted and starts performing normally after the first rx_cell_start after trstproc. from then on rx_cell_start must occur every 118 clocks. if an invalid rx_cell_start (that is, one that is not exactly 118 clocks after the preceding rx_cell_start) is received by the device (as occurs, for example, after a switchover), the first rx_cell_start is ignored and processing starts with the next rx_cell_start. figure 65. reset timing symbol parameter signals min max unit tres reset assertion time. /reset 40 se_clk periods trstproc reset processing time. /reset 60 se_clk periods tres tres trstproc trstproc /reset(i) se_clk(i) rx_cell_start(i)
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 97 figure 66 shows the timing for the jtag port. the /jtag_reset signal is asynchronous to jtag_tck. figure 66. jtag timing symbol parameter signals min max unit jtag_tck frequency 1 mhz tch jtag_tck high 80 ns tcl jtag_tck low 80 ns tjh jtag_tck hold time jtag_tms, jtag_tdi 40 ns tjres /jtag_reset low /jtag_reset 80 ns tjsu jtag_tck setup time jtag_tms, jtag_tdi 40 ns tjq jtag_tck-to-output delay /jtag_reset-to-output delay jtag_tdo 2.3 40 ns tch tcl tch tcl tjres tjres tjsu tjh tjsu tjh tjq tjq jtag_tck(i) /jtag_reset(i) jtag_tms(i) jtag_tdi(i) jtag_tdo(o)
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 98 7 microprocessor ports 7.1 microprocessor ports summary notes: ? the external /reset signal resets all microprocessor write ports to 0 when asserted. ? all ports marked as reserved must be initialized to 0 (unless otherwise indicated) at initial setup. software modifications to these locations after setup may cause incorrect operation. ? all read/write port bits marked not used must be written with the value 0 to maintain software com- patibility with future versions. ? most read-only bits marked not used are driven with a 0; however, some may have an unpredictable value on reads. therefore, all read-only bits marked not used should be masked by the software on reads to maintain compatibility with future versions. table 23. microprocessor ports summary byte address long address name read or write description 0 h 0 h revision r contains the device part number and revision. 4 h 1 h reset r/w resets the device, except the microprocessor interface. 8 h 2 h test_config r/w define various test/diagnostic functions. c h 3 h sram_config r/w defines the sram configuration. 10 h 4 h switch_config r/w defines the type of switch fabric. 14 h 5 h ram bist result r/w ram bist completion result 14 h -18 h 5 h -6 h not used r/w set to 0 for software compatibility with future devices. 1c h 7 h marked_cells_count r indicates the number of cells modulo (mod) 16 that had tag(9,1) set to 1, sent to or from the switch fabric. 20 h 8 h condition_pres_bits r defines the condition of present bits. 24 h 9 h condition_latch_bits r defines the condition of latch bits. 28 h a h intr_mask r/w defines the interrupt mask bits. 2c h -3c h b h -f h reserved r/w do not initialize. 40 h 10 h utopia_config r/w defines the mode of the utopia interface. 44 h 11 h ut_priority r/w indicates the priority of each virtual input/output. 48 h 12 h ut_enable r/w enables whether the polling results from the phy layer device will be considered during the utopia phy selection mechanism. also sets the number of devices to be polled when standard polling is used. 4c h 13 h tx_ut_stat r indicates the transmit utopia status. 50 h 14 h tx_ut_wd_alive r/w indicates the transmit utopia watchdog liveness. 54 h -7f h 15 h -1f h not used r driven with a 0. mask on reads to maintain compatibil- ity with future versions. 80 h 20 h rx_cell_start_align r/w contains alignment value for the internal rxcellstart signal from the external rx_cell_start.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 99 84 h -9c h 21 h -27 h not used r driven with a 0. mask on reads to maintain compatibil- ity with future versions. a0 h 28 h rx_queue_engine_test r/w receive queue engine test/debug register. a4 h 29 h tx_queue_engine_test r/w transmit queue engine test/debug register. a8 h 2a h queue_engine_condi tion_pres_bits r current status of queue engine failure detection bits. ac h 2b h queue_engine_conditi on_latch_bits r/w latched version of queue engine failure detection bits. b0 h 2c h queue_engine_int_mas k r/w interrupt mask for the queue engine failure detection bits. b4 h -fc h 2d h -3f h not used r driven with a 0. mask on reads to maintain compatibil- ity with future versions. 100 h - 7bffc h 40 h - 1effff h not used driven with a 0. mask on reads to maintain compatibil- ity with future versions. 7c0000 h 1f0000 h rx_dir_config r/w sets the congestion threshold for the receive direction. 7c0004 h 1f0001 h rx_dir_state r/w indicates the current queue depth for this sc. 7c0008 h - 7c001f h 1f0002 h - 1f0007 h reserved r do not initialize. 7c0020 h 1f0008 h tx_dir_config r/w sets the congestion threshold for the transmit direction. 7c0024 h or 7c00a4 h 1f0009 h or 1f0029 h tx_dir_state r/w indicates the current state of the transmit direction. 7c0028 h - 7c003c h 1f000a h - 1f000f h reserved r do not initialize. 7c0040 h 1f0010 h rx_sent_cells r twenty-four-bit counter of cells sent in the receive direction. 7c0044 h 1f0011 h rx_dropped_cells r twenty-four-bit counter of cells dropped in the receive direction. 7c0048 h 1f0012 h tx_sent_cells r twenty-four-bit counter of cells sent in the transmit direction. 7c004c h 1f0013 h tx_dropped_cells r twenty-four-bit counter of cells dropped in the transmit direction. 7c0050 h 1f0014 h rx_lower16_scg_confi g r/w configuration of the rx lower 16 service class group. 7c0054 h 1f0015 h rx_lower16_scg_state r/w state of the rx lower 16 service class group. 7c0058 h 1f0016 h rx_lower32_scg_confi g r/w configuration of the rx lower 32 service class group. 7c005c h 1f0017 h rx_lower32_scg_state r/w state of the rx lower 32 service class group. table 23. microprocessor ports summary (continued) byte address long address name read or write description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 100 7c0060 h 1f0018 h rx_lower48_scg_confi g r/w configuration of the rx lower 48 service class group. 7c0064 h 1f0019 h rx_lower48_scg_state r/w state of the rx lower 48 service class group. 7c0068 h 1f001a h tx_lower4_scg_config r/w configuration of the tx lower 4 service class group. 7c006c h 1f001b h tx_lower4_scg_state r/w state of the tx lower 4 service class group. 7c0070 h 1f001c h tx_lower8_scg_config r/w configuration of the tx lower 8 service class group. 7c0074 h 1f001d h tx_lower8_scg_state r/w state of the tx lower 8 service class group. 7c0078 h 1f001e h tx_lower12_scg_confi g r/w configuration of the tx lower 12 service class group. 7c007c h 1f001f h tx_lower12_scg_state r/w state of the tx lower 12 service class group. 7c0080 h - 7c01fc h 1f0020 h - 1f007f h reserved r do not initialize. table 23. microprocessor ports summary (continued) byte address long address name read or write description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 101 7.2 microprocessor ports bit definitions 7.2.1 revision this register contains the device part number and revision. address: 0 h (0 h byte) type: read-only format: refer to the following table. 7.2.2 reset address: 1 h (4 h byte) type: read/write format: refer to the following table. field (bits) description not used (31:16) driven with a 0. mask on reads to maintain compatibility with future versions. part_type (15:4) indicates the part number. always returns 487 h . revision (3:0) driven with a 1 h to indicate the second qrt version. field (bits) description not used (31:2) write with a 0 to maintain software compatibility with future versions. hw_reset (1) 1 resets the device to a state similar to that resulting from asserting the /reset pin, except the microprocessor registers are available. the internal or external rams are not available. this allows the basic mode of the device to be initialized before the i/o is enabled. 0 this reset is deasserted. resets to 1 b . sw_reset (0) 1 resets the device, except for the microprocessor interface. the processor may initialize all the registers and internal memories without the cell flow while this is asserted. the switch fabric and utopia interface are running, but there is no cell flow. 0 normal operation. resets to 1 b .
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 102 7.2.3 test_config address: 2 h (8 h byte) type: read/write format: refer to the following table. field (bits) description not used (31:22) write with a 0 to maintain software compatibility with future versions. vo ram bist control (21:20) 00 normal operation. 01 bist memory test mode. ram bist controller will begin testing the vo ram. this value must be maintained until the vo_ram_complete bit in the bist_result register is 1. 10 bist controller test mode. perform the controller error detector test. the vo_ram_bist_fail bit will be set to 1 at the end of this operation 11 invalid control code. do not use resets to 00 b . rs ram bist control (19:18) 00 normal operation. 01 bist memory test mode. ram bist controller will begin testing the rs ram. this value must be maintained until the rs_ram_complete bit in the bist_result register is 1. 10 bist controller test mode. perform the controller error detector test. the rs_ram_bist_fail bit will be set to 1 at the end of this operation 11 invalid control code. do not use resets to 00 b . ts ram bist control (17:16) 00 normal operation. 01 bist memory test mode. ram bist controller will begin testing the ts ram. this value must be maintained until the ts_ram_complete bit in the bist_result register is 1. 10 bist controller test mode. perform the controller error detector test. the ts_ram_bist_fail bit will be set to 1 at the end of this operation 11 invalid control code. do not use resets to 00 b . rf ram bist control (15:14) 00 normal operation. 01 bist memory test mode. ram bist controller will begin testing the rf ram. this value must be maintained until the rf_ram_complete bit in the bist_result register is 1. 10 bist controller test mode. perform the controller error detector test. the rf_ram_bist_fail bit will be set to 1 at the end of this operation 11 invalid control code. do not use resets to 00 b .
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 103 tf ram bist control (13:12) 00 normal operation. 01 bist memory test mode. ram bist controller will begin testing the tf ram. this value must be maintained until the rf_ram_complete bit in the bist_result register is 1. 10 bist controller test mode. perform the controller error detector test. the tf_ram_bist_fail bit will be set to 1 at the end of this operation 11 invalid control code. do not use resets to 00 b . not used (11:10) write with a 0 to maintain software compatibility with future versions. reserved (9) write with a 0 to maintain future software compatibility. resets to 0. reserved (8) write with a 0 to maintain future software compatibility. resets to 0. not used (7:6) write with a 0 to maintain software compatibility with future versions. utop_loop (5) note: for ut loopback, the device must be in oc_12c_mode (refer to rx_oc_12c_mode on page 118 ), and the atm_clk in the qrt must be synchronously derived from the sysclk. 1 loopback cells from receive utopia to transmit utopia. 0 normal operation. resets to 0 b . sf_loop (4) note: for sf loopback, the device must not use randomization (set disable_randomization = 1; refer to disable_randomization on page 107 ) and turn off the complex phase aligners (set cpa_off = 1; refer to cpa_off on page 107 ). 1 loopback at the switch fabric interface. 0 normal operation. resets to 0 b . not used (3:1) write with a 0 to maintain software compatibility with future versions. reserved (0) resets to 0. field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 104 7.2.4 sram_config address: 3 h (c h byte) type: read/write format: refer to the following table. field (bits) description not used (31:24) write with a 0 to maintain software compatibility with future versions. rx_dram_type (23) 1 using 1m 16 sdram or 1m x 32 sgram devices. for the function of / rx_dram_cs(1:0), refer to /rx_dram_cs(1:0) on page 69 . . 0 using 256k 32 sgram devices. tx_dram_type (22) 1 using 1m 16 sdram or 1m x 32 sgram devices. for the function of / tx_dram_cs(1:0), refer to /tx_dram_cs(1:0) on page 70 . 0 using 256k 32 sgram devices. not used (21:14) write with a 0 to maintain software compatibility with future versions. num_vi (13:12) defines the number of virtual input (vi) bits to use to determine the index into the vi_vpi_table (refer to section 9.2.1 vi_vpi_table starting on page 175 ) as part of the channel lookup. 0 h use zero vi bits. use only the vp bits in the calculation for the vi_vpi_table. only utopia address 0 may be used in this mode. 1 h use two vi bits (1:0) as the two msbs in the calculation of the index for the vi_vpi_table. only utopia addresses 0-3 may be used in this mode. 2 h use five vi bits (4:0) as the five msbs in the calculation of the index for the vi_vpi_table. any of the 31 utopia addresses may be used in this mode. 3 h not defined. resets to 0 h . alram_type (11) 1 using the single cycle deselect (scd) type ssram for alram with alram_config = 3. note: this is only valid when the alram is populated with 2 chips of 256k x 18 type. 0 using the double cycle deselect (dcd) type ssram for alram resets to 0 h not used (10) write with a 0 to maintain software compatibility with future versions.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 105 al_ram_config (9:8) defines the size of the sram used to store the address translation tables and a number of other tables. the processor must know or determine the sram size. then, the processor must inform the device of the sram size by configuring this field. initialize to the proper setting. 0 h al_ram = 64k 16 ssram. 8k vi_vpi_table (13 bits). sum of vi and vp bits. refer to section 9.2.1 vi_vpi_table starting on page 175. 4k vci_table (12 bits). refer to vci_table on page 176 . 4k service table. 8k multicast input pointer fifos 2 8 512. 16k multicast cell output pointer fifos 2 8 32 32. 8k transmit cell buffer linked list (one-half of the phy). 8k receive cell buffer linked list. 1 h al_ram = 128k 16 ssram. 16k vi_vpi_table (14 bits). 16k vci_table (14 bits). 4k service table. 16k multicast input pointer fifos 2 8 1k. 16k multicast cell output pointer fifos 2 8 32 32. 16k transmit cell buffer linked list. 16k receive cell buffer linked list. 2 h al_ram = 256k 16 ssram. 32k vi_vpi_table (15 bits). 32k vci_table (15 bits). 4k service table. 16k multicast cell output pointer fifos 2 8 32 32. 16k multicast input pointer fifos 2 8 2k. 16k or 32k transmit cell buffer linked list. 16k or 32k or 64k receive cell buffer linked list. 3 h al_ram = 512k 16 ssram. 128k vi_vpi_table (17 bits). 64k vci_table (16 bits). 4k service table. 32k multicast input pointer fifos 2 8 2k. 32k multicast cell output pointer fifos 2 8 32 64. 16k or 32k or 64k transmit cell buffer linked list. 16k or 32kor 64k receive cell buffer linked list. resets to 0 b . not used (7:2) write with a 0 to maintain software compatibility with future versions. ch_ram_config (1:0) defines the size of the sram used by the channel tables. the processor must know or determine the sram size. then, the processor must inform the device of the sram size by configuring this field. initialize to the proper setting. this setting has no effect on the qrt operation, but it may in a future qrt device version. 0 h ch_ram = 32k 32 ssram. 2k channels. 1 h ch_ram = 64k 32 ssram. 4k channels. 2 h ch_ram = 128k 32 ssram. 8k channels. 3 h ch_ram = 256k 32 ssram. 16k channels. resets to 0 b . (continued) field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 106 7.2.5 switch_config address: 4 h (10 h byte) type: read/write format: refer to the following table. field (bits) description not used (31:20) write with a 0 to maintain software compatibility with future versions. enable_port(3:0) (19:16) bit 19 corresponds to port 3, bit 18 corresponds to port 2, bit 17 corresponds to port 1 and bit 16 corresponds to port 0 as follows: 1 enable the switch fabric port, and allow cells to be sent to it. also, if sf_loop (refer to sf_loop on page 103 ) is asserted, replicate the looped back cells out onto the switch fabric. 0 disable the switch fabric port. send no cells to it. resets to 0. clear_upper_vpi (15) 1 clears vpi(11:8) bits for all incoming (rx) cells 0 not clear vpi(11:8) bits for all incoming (rx) cells resets to 0. enforce_unused_vci (14) 1 drop cells with any non-zero value set in the unused vci bits. 0 do not check for non-zero value in the unused vci bits resets to 0. tx_count_sent_clp (13) 1 store the clp = 0 sent cells in tx_cells_sent. store the clp = 1 sent cells in tx_ch_cells_dropped for all channels (refer to tx_ch_cells_sent on page 193 and tx_ch_cells_drpd on page 193 ). 0 use the tx_cells_sent and tx_ch_cells_drpd counters as docu- mented in tx_ch_cells_sent on page 193 and tx_ch_cells_drpd on page 193 respectively. reserved (12:8) initialize to 0 at initial setup. software modifications to these locations after setup may cause incorrect operation. time_slot_priority (7) 1 automatically increment the rx_ch_switch_group rx_ch_config on page 184 by 1 (1 to 2, and 2 to 3, 3 will not be incremented) when an unicast cell was selected from the rx_service_table ( rx_service_table on page 182) . rx_ch_switch_group is used to set the priority(1:0) field in the se_d_out qrt-qse interface cell format. on page 91 nibble 1. 0 use the rx_ch_switch_group value for priority rx_ch_config on page 184 resets to 0. global_sf_spare (6) 1 set the sf_spare ( qrt-qse interface cell format. on page 91) bit to 1 (nibble 0 of the se_d_out) for all cells sent to the switch fabric 0 use the rx_ch_sf_spare rx_ch_config on page 184 value in the rx_ch_config(4) word for the sf_spare bit resets to 0.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 107 separate_out_mc (5) 1 treat switch fabric outputs as separate outputs for multicast traffic. 0 group switch fabric outputs as a single output for multicast traffic. resets to 0. reserved (4) initialize to 0 at initial setup. software modifications to this location after setup may cause incorrect operation. resets to 0. parity_fail_dis (3) 1 disable parity checking on the switch fabric. 0 enable parity checking on the switch fabric. resets to 0. cpa_off (2) 1 turn off complex phase aligner at the switch fabric interface. 0 use complex phase aligner to retime signals at the switch fabric interface. resets to 0. disable_randomizatio n (1) 1 disable the randomization at the switch fabric interface. 0 enable the randomization at the switch fabric interface. reserved (0) initialize to 1 at initial setup. software modifications to this location after setup may cause incorrect operation. resets to 0. field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 108 7.2.6 ram bist result address: 5 h (14 h byte) type: read/write format: refer to the following table. field (bits) description not used (31:21) write with a 0 to maintain software compatibility with future versions. tf_ram_bist_fail (20) if tf_ram_bist_control is set to 01 b 0 ram bist memory test has passed. 1 ram bist memory test has failed. if tf_ram_bist_control is set to 10 b 0 ram bist controller test has failed. 1 ram bist controller test has passed. note: this bit must be cleared by writing a 0 before executing the ram_bist memory or controller tests. resets to 0 b . rf_ram_bist_fail (19) if rf_ram_bist_control is set to 01 b 0 ram bist memory test has passed. 1 ram bist memory test has failed. if rf_ram_bist_control is set to 10 b 0 ram bist controller test has failed. 1 ram bist controller test has passed. note: this bit must be cleared by writing a 0 before executing the ram_bist memory or controller tests. resets to 0 b . vo_ram_bist_fail (18) if vo_ram_bist_control is set to 01 b 0 ram bist memory test has passed. 1 ram bist memory test has failed. if vo_ram_bist_control is set to 10 b 0 ram bist controller test has failed. 1 ram bist controller test has passed. note: this bit must be cleared by writing a 0 before executing the ram_bist memory or controller tests. resets to 0 b .
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 109 rs_ram_bist_fail (17) if rs_ram_bist_control is set to 01 b 0 ram bist memory test has passed. 1 ram bist memory test has failed. if rs_ram_bist_control is set to 10 b 0 ram bist controller test has failed. 1 ram bist controller test has passed. note: this bit must be cleared by writing a 0 before executing the ram_bist memory or controller tests. resets to 0 b . ts_ram_bist_fail (16) if ts_ram_bist_control is set to 01 b 0 ram bist memory test has passed. 1 ram bist memory test has failed. if ts_ram_bist_control is set to 10 b 0 ram bist controller test has failed. 1 ram bist controller test has passed. note: this bit must be cleared by writing a 0 before executing the ram_bist memory or controller tests. resets to 0 b . not used (15:5) write with a 0 to maintain software compatibility with future versions. tf_ram_bist_complete (4) 0 tf_ram_bist memory test is in progress 1 tf_ram_bist memory test has completed resets to 0 b . rf_ram_bist_complete (3) 0 rf_ram_bist memory test is in progress 1 rf_ram_bist memory test has completed resets to 0 b . vo_ram_bist_complete (2) 0 vo_ram_bist memory test is in progress 1 vo_ram_bist memory test has completed resets to 0 b . rs_ram_bist_complete (1) 0 rs_ram_bist memory test is in progress 1 rs_ram_bist memory test has completed resets to 0 b . ts_ram_bist_complete (0) 0 ts_ram_bist memory test is in progress 1 ts_ram_bist memory test has completed resets to 0 b . field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 110 7.2.7 marked_cells_count tx_marked_cells is a 4-bit counter for each of the four switch fabric input ports. tx_marked_cells counts cells that have the mb set in their tag. rx_marked_cells is a 4-bit counter for each of the four switch fabric output ports. rx_marked_cells counts cells that have the mb set in their tag. address: 7 h (1c h byte) type: read-only format: refer to the following table. field (bits) description tx_marked_cells(3) (31:28) the number of cells mod 16 with the mb set in the tag that were received through se_d_in(3,3:0). tx_marked_cell(2) (27:24) the number of cells mod 16 with the mb set in the tag that were received through se_d_in(2,3:0). tx_marked_cells(1) (23:20) the number of cells mod 16 with the mb set in the tag that were received through se_d_in(1,3:0). tx_marked_cells(0) (19:16) the number of cells mod 16 with the mb set in the tag that were received through se_d_in(0,3:0). rx_marked_cells(3) (15:12) the number of cells mod 16 that were successfully transmitted out of se_d_out(3,3:0). rx_marked_cells(2) (11:8) the number of cells mod 16 that were successfully transmitted out of se_d_out(2,3:0). rx_marked_cells(1) (7:4) the number of cells mod 16 that were successfully transmitted out of se_d_out(1,3:0). rx_marked_cells(0) (3:0) the number of cells mod 16 that were successfully transmitted out of se_d_out(0,3:0).
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 111 7.2.8 condition_pres_bits each interrupt has a condition present bit that indicates the condition is present now. some fail- ures are transitory, so this bit may read clear even though the condition is occurring frequently. address: 8 h (20 h byte) type: read-only. all bits reset to 0, unless otherwise specified. format: refer to the following table. field (bits) description ack_live_fail (31:28) bit 31 corresponds to port 3, bit 30 corresponds to port 2, bit 29 corresponds to port 1 and bit 28 corresponds to port 0 as follows: 1 no ack, mnack, or onack was received on the same cell time that a unicast cell was sent. this indicates that the end-to-end path may be bad. 0 normal operation. refer to unacknowledged cell detection on page 48 , liveness of backpressure sig- nal on page 48 , bp_ack remote failure detection on page 50 , and to table 2 on page 50 for more information about the ack_live_fail interrupt. ut_soc_fail (27) 1 failure was detected on the ratm_soc signal. 0 normal operation. ut_clk_fail (26) 1 failure was detected on the utopia clock (atm_clk). 0 normal operation. sf_clk_fail (25) 1 failure was detected on the switch fabric clock (se_clk). 0 normal operation. rx_utop_hec_fail (24) 1 the last hec on the receive utopia interface was bad. 0 the last hec on the receive utopia interface was good. rx_dram_parity_fail (23) 1 the last parity check on the rx_dram was bad. 0 the last parity check on the rx_dram was good. tx_dram_parity_fail (22) 1 the last parity check on the tx_dram was bad. 0 the last parity check on the tx_dram was good. al_ram_parity_fail (21) 1 the last parity check on the al_ram was bad. 0 the last parity check on the al_ram was good. ch_ram_parity_fail (20) 1 the last parity check on the ch_ram was bad. 0 the last parity check on the ch_ram was good. tx_parity_fail (19:16) bit 19 corresponds to port 3, bit 18 corresponds to port 2, bit 17 corresponds to port 1 and bit 16 corresponds to port 0 as follows: 1 the transmit parity calculated over the first 12 nibbles of the cell header coming into the qrt on se_d_in#(3:0) was bad during the last valid cell time. 0 the transmit parity was good during the last valid cell time. bp_ignored (15) 1 the backpressure was ignored during the last cell time, because a cell was received in violation of the backpressure that had been given. 0 the backpressure was not ignored during the last cell time.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 112 se_input_port_fail (14:11) bit 14 corresponds to port 3, bit 13 corresponds to port 2, bit 12 corresponds to port 1 and bit 11 corresponds to port 0 as follows: 1 indicates one of the following: ? no soc or 10 pattern was present on a switch fabric port input, or ? invalid cell code, or ? bad idle cell code, or ? fabric out of synch. 0 the switch fabric input was normal. refer to soc coding on page 47 , soc inversions on page 47 , redundant cell present coding on page 47 , idle cell pattern checking on page 47 , table 3 on page 51, and to table 5 on page 52 for more information about the se_input_port_fail interrupt. bp_remote_fail (10:7) bit 10 corresponds to port 3, bit 9 corresponds to port 2, bit 8 corresponds to port 1 and bit 7 corresponds to port 0 as follows: 1 the forward data path from the qrt to the qse was found to be bad through signaling on the bp_ack_in(3:0) line. 0 the forward data path from the qrt to the qse was good. refer to remote data path failure indication on page 48 , liveness of backpressure signal on page 48 , bp_ack remote failure detection on page 50 , table 2 on page 50 , and to table 4 on page 52 for more information about the bp_remote_fail interrupt. bp_ack_fail (6:3) bit 6 corresponds to port 3, bit 5 corresponds to port 2, bit 4 corresponds to port 1 and bit 3 corresponds to port 0 as follows: 1 bp_ack_in(3:0) did not have the special code. 0 bp_ack_in(3:0) had the special code. refer to liveness of backpressure signal on page 48 , bp_ack_in pattern check- ing on page 49 , bp_ack inversion checking on page 49 , table 2 on page 50 , and to table 4 on page 52 for more information about the bp_ack_fail interrupt. out_wd_int (2) 1 at least one of the utopia output watchdogs is currently expired. 0 none of the utopia output watchdogs is currently expired. eqd_int (1) 1 the device is in the empty congestion state. 0 the device is not in the empty congestion state. reserved (0) initialize to 0 at initial setup. software modifications to these locations after setup may cause incorrect operation. (continued) field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 113 7.2.9 condition_latch_bits each interrupt has a latch bit indicating there has been a failure detected since the last time that the latch word was read. address: 9 h (24 h byte) type: read-only C cleared on read. reset value: all bits reset to 0, unless specified. format: refer to the following table. field (bits) description ack_fail_latch (31:28) bit 31 corresponds to port 3, bit 30 corresponds to port 2, bit 29 corresponds to port 1 and bit 28 corresponds to port 0 as follows: 1 no ack, mnack, or onack was received on the same cell time that a unicast cell was sent. 0 normal operation. refer to section 3 fault tolerance starting on page 44 for more information. ut_soc_fail_latch (27) 1 failure was detected on the ratm_soc signal. 0 normal operation. ut_clk_fail_latch (26) 1 failure was detected on the utopia clock (atm_clk). 0 normal operation. sf_clk_fail_latch (25) 1 failure was detected on the switch fabric clock (se_clk). 0 normal operation. rx_utop_hec_fail_latch (24) 1 the hec of the receive utopia interface was bad at least once since this latch was read. 0 the hec of the receive utopia interface was good every time it was measured since this latch was read. rx_dram_parity_fail_latch (23) 1 the parity of the rx_dram was bad at least once since this latch was read. 0 the parity of the rx_dram was good every time it was measured since this latch was read. tx_dram_parity_fail_latch (22) 1 the parity of the tx_dram was bad at least once since this latch was read. 0 the parity of the tx_dram was good every time it was measured since this latch was read. al_ram_parity_fail_latch (21) 1 the parity of the al_ram was bad at least once since this latch was read. 0 the parity of the al_ram was good every time it was measured since this latch was read. ch_ram_parity_fail_latch (20) 1 the parity of the ch_ram was bad at least once since this latch was read. 0 the parity of the ch_ram was good every time it was measured since this latch was read. tx_parity_fail_latch (19:16) bit 19 corresponds to port 3, bit 18 corresponds to port 2, bit 17 corresponds to port 1 and bit 16 corresponds to port 0 as follows: 1 the transmit parity calculated over the first 12 nibbles of the cell header coming into the qrt on se_d_in#(3:0) was bad at least once since this latch was read. 0 the transmit parity was good in every cell since this latch was read.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 114 bp_ignored_fail_latch (15) 1 backpressure was ignored at least once since this latch was read. 0 backpressure was not ignored since this latch was read. refer to section 3 fault tolerance starting on page 44 for more information. se_input_port_fail_latch (14:11) bit 14 corresponds to port 3, bit 13 corresponds to port 2, bit 12 corresponds to port 1 and bit 11 corresponds to port 0 as follows: 1 one of the following was detected at least once since this latch was read: ? bad soc pattern ? invalid cell code ? bad idle cell code ? fabric out of synch 0 none of the above has been detected since this latch was read. refer to section 3 fault tolerance starting on page 44 for more information. bp_remote_fail_latch (10:7) bit 10 corresponds to port 3, bit 9 corresponds to port 2, bit 8 corresponds to port 1 and bit 7 corresponds to port 0 as follows: 1 the forward data path was bad at least once since this latch was read. 0 the forward data path was not bad at least once since this latch was read. refer to section 3 fault tolerance starting on page 44 for more information. bp_ack_fail_latch (6:3) bit 6 corresponds to port 3, bit 5 corresponds to port 2, bit 4 corresponds to port 1 and bit 3 corresponds to port 0 as follows: 1 the bp_ack_in(3:0) line did not have the required pattern at least once since this latch was read. 0 the bp_ack_in(3:0) line did have the required pattern at least once since this latch was read. out_wd_int_latch (2) 1 at least one of the utopia output watchdogs expired since the last time this register was read. 0 none of the utopia output watchdogs expired since the last time this register was read. eqd_int_latch (1) 1 the empty queue depth threshold was crossed in either direction since this latch was read. 0 the empty queue depth threshold was not crossed in either direction since this latch was read. the congestion is declared to have been relieved when the queue depth crossed back above twice the configured congestion threshold. reserved (0) initialize to 0 at initial setup. software modifications to these locations after setup may cause incorrect operation. (continued) field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 115 7.2.10 intr_mask each interrupt has a mask bit that prevents the interrupt pin (/intr) from being asserted, even though the corresponding latch bit is set. address: a h (28 h byte) type: read/write reset value:1 format: refer to the following table. field (bits) description mask_ack_fail (31:28) bit 31 corresponds to port 3, bit 30 corresponds to port 2, bit 29 corresponds to port 1 and bit 28 corresponds to port 0 as follows: 1 mask the ack_live_fail interrupt (refer to ack_live_fail on page 111 ). 0 enable ack_live_fail. mask_ut_soc_fail (27) 1 mask the receive atm soc fail interrupt (refer to ut_soc_fail on page 111 ). 0 normal operation. mask_ut_clk_fail (26) 1 mask the utopia clock fail interrupt (refer to ut_clk_fail on page 111 ). 0 enable the utopia clock fail interrupt. mask_sf_clk_fail (25) 1 mask the switch fabric clock fail interrupt (refer to sf_clk_fail on page 111 ). 0 enable the switch fabric clock fail interrupt. mask_rx_utop_hec_fail (24) 1 mask the receive utopia hec fail interrupt (refer to rx_utop_hec_fail on page 111 ). 0 enable the receive utopia hec fail interrupt. mask_rx_ram_parity_fail (23) 1 mask the receive ram parity fail interrupt (refer to rx_dram_parity_fail on page 111 ). 0 enable the rx ram parity fail interrupt. mask_tx_ram_parity_fail (22) 1 mask the transmit ram parity fail interrupt (refer to tx_dram_parity_fail on page 111 ). 0 enable the tx ram parity fail interrupt. mask_al_ram_parity_fail (21) 1 mask the al ram parity fail interrupt (refer to al_ram_parity_fail on page 111 ). 0 enable the al ram parity fail interrupt. mask_ch_ram_parity_fail (20) 1 mask the ch ram parity fail interrupt (refer to ch_ram_parity_fail on page 111 ). 0 enable the ch ram parity fail interrupt. mask_tx_parity_fail (19:16) bit 19 corresponds to port 3, bit 18 corresponds to port 2, bit 17 corresponds to port 1 and bit 16 corresponds to port 0 as follows: 1 mask the transmit parity fail interrupt (refer to tx_parity_fail on page 111 ). 0 enable the transmit parity fail interrupt. mask_bp_ignored (15) 1 mask the backpressure ignored interrupt (refer to bp_ignored on page 111 ). 0 enable the backpressure ignored interrupt.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 116 mask_se_input_port_fail (14:11) bit 14 corresponds to port 3, bit 13 corresponds to port 2, bit 12 corresponds to port 1 and bit 11 corresponds to port 0 as follows: 1 mask the switch element input port interrupt (refer to se_input_port_fail on page 112 ). 0 enable the switch element input port interrupt. mask_bp_remote_fail (10:7) bit 10 corresponds to port 3, bit 9 corresponds to port 2, bit 8 corresponds to port 1 and bit 7 corresponds to port 0 as follows: 1 mask the backpressure remote fail interrupt (refer to bp_remote_fail on page 112 ). 0 enable the backpressure remote fail interrupt. mask_bp_ack_fail (6:3) bit 6 corresponds to port 3, bit 5 corresponds to port 2, bit 4 corresponds to port 1 and bit 3 corresponds to port 0 as follows: 1 mask the backpressure fail interrupt (refer to bp_ack_fail on page 112 ). 0 enable the backpressure fail interrupt. mask_out_wd_int (2) 1 mask the output watchdog interrupt (refer to out_wd_int on page 112 ). 0 enable the output watchdog interrupt. mask_eqd_int (1) 1 mask the empty queue depth interrupt (refer to eqd_int on page 112 ). 0 enable the empty queue depth interrupt. reserved (0) set to 1 for future software compatibility. (continued) field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 117 7.2.11 utopia_config the utopia_config register configures both the receive and transmit utopia interface dur- ing reset. since this register initializes an internal state machine, alteration during non-reset con- ditions is not recommended. the transmit utopia watchdog is configured from this register as well as the use of outchan insertion in the outgoing cells. the msp_mode bit selects between the following polling methods: ? utopia level 2 standard polling that uses a single cell available signal (tatm_clav(0) and ratm_clav(0)). ? utopia level 2 optional msp that uses four cell available signals (tatm_clav(3:0) and ratm_clav(3:0)) to poll as many as 31 devices in one cell time. the chk_hec bit enables the checking of the hec of incoming cells. if the device finds a hec error, an interrupt is asserted and the cell is dropped in the receive utopia block. note: the backplane_mode bit was excluded from the qrt testing program. the tx_oc_12c_mode, rx_oc_12c_mode, and utopia_2 bits allow the user to select the configuration of receive and transmit side interfaces independently. the *_oc_12c_mode bits take precedence over the utopia_2 bit. for example, for a qrt configured to be rx_oc_12c_mode and not tx_oc_12c_mode and utopia_2, the interface treats the receive side as a single-phy interface and the transmit side as a multi-phy interface requiring addressing. this feature is useful when interfacing to the pmc-sierra pm7322 rcmp-800 device. table 24 explains all combination of these bits. table 24. various ways to configure utopia interface utopiaconfig(2:0) explanation 111 tx and rx side configured for single phy. 110 tx and rx side configured for single phy. 101 tx side configured for single phy, rx side configured for mphy. 100 tx and rx side configured for single phy. 011 tx side configured for mphy, rx side configured for single phy. useful for rcmp applications. 010 tx and rx side configured for single phy. 001 tx and rx side configured for mphy. 000 tx and rx side configured for single phy.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 118 address: 10 h (40 h byte) type: read/write format: refer to the following table. field (bits) description not used (31:10) driven with a 0. mask on reads to maintain software compatibility with future versions. wd_time (9:8) the period during which time the tatm_clav(3:0) must be asserted for a given output. initialize to a setting that allows the slowest phy device attached to the utopia interface to respond in time. 0 h set to a setting tolerant to ds0 outputs; tolerance equals 52,000 cell times. 1 h set to a setting tolerant to ds1 outputs; tolerance equals 5000 cell times. 2 h set to a setting tolerant to oc-3 outputs; tolerance equals 32 cell times. 3 h disable the watchdog. resets to 00 b . out_chan_insertion (7) 1 insert tx output channel number in the 16 bit hec/udf field to be used downstream 0 insert ffffh in the hec/udf field . resets to 0. tdm (6) 1 perform utopia tdm plus servicing. the tdm feature provides an addi- tional level of servicing to compliment 2-level priority servicing . the suite of phy addresses included in the tdm table is based on utenable 0 perform only 2-level priority servicing . resets to 0. msp_mode (5) 1 perform msp (four cell available lines used). use this setting when using direct status indication. 0 perform utopia level 2 mphy standard polling (one cell available line used). resets to 0. chk_hec (4) 1 check the hec of incoming cells. 0 ignore the hec of incoming cells. use this setting when connecting to devices that do not drive the proper hec on the utopia bus or when the hec field is used for other purposes. resets to 0. backplane_mode (3) note: this feature was excluded from the qrt testing program. 1 allow extra latency across the utopia interface necessary to implement a 25 mhz (maximum) backplane. 0 use normal utopia level 2 timing. resets to 0. tx_oc_12c_mode (2) 1 the device is connected to an oc-12c line at transmit utopia address 0. this overrides the setting of the utopia_2 bit. 0 the device is connected to a normal transmit utopia level 2 interface. resets to 0. rx_oc_12c_mode (1) 1 the device is connected to an oc-12c line at receive utopia address 0. this overrides the setting of the utopia_2 bit. 0 the device is connected to a normal receive utopia level 2 interface. resets to 0.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 119 7.2.12 ut_priority the utopia interface provides at the very least, 2-level priority assignment scheme. ut_priority configures each utopia interface to belong to either the high bandwidth or low bandwidth category. phy devices with ut_priority = 1 are serviced with strict priority over phy devices with ut_priority = 0. phy devices within each bandwidth category are served lowest numbered phy device address first. this register is configurable independent of software reset and can be changed during cell flow. address: 11 h (44 h byte) type: read/write format: refer to the following table. utopia_2 (0) 1 the interface is in utopia level 2 mode. 0 the interface is in utopia level 1 mode. resets to 0. field (bits) description not used (31) write with a 0 to maintain software compatibility with future versions. phy devices16- 30 are defined to be at low priority. ut_priority (30) 1 service phy device 30 at high priority. 0 service phy device 30 at low priority. ut_priority (29) 1 service phy device 29 at high priority. 0 service phy device 29 at low priority. . . . . . . ut_priority (0) 1 service phy device 0 at high priority. 0 service phy device 0 at low priority. (continued) field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 120 7.2.13 ut_enable the ut_enable register enables whether or not the polling results from the phy device will be considered during the utopia phy device selection mechanism. the ut_enable register is also used to set the number of devices that will be polled when the standard polling method is used. enabling only the devices that are used and configuring the system so the device addresses are grouped together in the lower address range provides the best results for the implemented standard polling algorithm. for msp mode, all devices are polled regardless of whether or not they are enabled, but again, the enable is used to mask out those that are either not on the bus or are turned off. this register is configurable independent of software reset and can be changed dur- ing cell flow. when the utopia_config tdm bit is set, the ut_enable register is also used to define the tdm priority pool. address: 12 h (48 h byte) type: read/write format: refer to the following table. a transition on any of these bits clears the corresponding entry in the tx_ut_wd_alive regis- ter (refer to tx_ut_wd_alive on page 121 ). field (bits) description not used (31) write with a 0 to maintain software compatibility with future versions. ut_enable (30) 1 enable cell transmission from phy device 30. 0 disable cell transmission from phy device 30. ut_enable (29) 1 enable cell transmission from phy device 29. 0 disable cell transmission from phy device 29. . . . . . . ut_enable (0) 1 enable cell transmission from phy device 0. 0 disable cell transmission from phy device 0.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 121 7.2.14 tx_ut_stat tx_ut_stat is a register that reflects the current polling status of the phy device requests for service. the register is used as an input to the transmit utopia watchdog register (refer to tx_ut_wd_alive on page 121 ). address: 13 h (4c h byte) type: read-only format: refer to the following table. 7.2.15 tx_ut_wd_alive the tx_ut_wd_alive bits in this register indicate a given phy device has indicated it would accept a cell within the wd_time (refer to wd_time on page 118 ) when polled. cells bound for phy devices that fail this test are flushed in the background. address: 14 h (50 h byte) type: read/write format: refer to the following table. field (bits) description not used (31) will be set to 0. mask for future software compatibility. tx_ut_stat (30) the phy device at address 30 is ready to receive a cell. tx_ut_stat (29) the phy device at address 29 is ready to receive a cell. . . . . . . tx_ut_stat (0) the phy device at address 0 is ready to receive a cell. field (bits) description not used (31) write with a 0 to maintain software compatibility with future versions. tx_ut_wd_alive (30) 1 the phy device at address 30 has responded to polling with an assertion of tatm_clav(3:0) for a period less than wd_time. 0 the phy device at address 30 has not responded to a poll with an assertion of tatm_clav(3:0) for a period longer than wd_time. phy device 30 has expired, therefore drain remaining cells intended for phy device 30 at lowest priority. tx_ut_wd_alive (29) 1 the phy device at address 29 has responded to polling with an assertion of tatm_clav(3:0) for a period less than wd_time. 0 the phy device at address 29 has not responded to a poll with an assertion of tatm_clav(3:0) for a period longer than wd_time. phy device 29 has expired, therefore drain remaining cells intended for phy device 29 at lowest priority. tx_ut_wd_alive (28:1) . . .
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 122 7.2.16 rx_cell_start_align (internal structure) rx_cell_start_align configures the delay for the internal rxcellstart signal by taking the external rx_cell_start signal, adding the 7-bit offset, and generating the internal rxcellstart signal. this allows flexibility and simplicity in the distribution of rx_cell_start to qrts on different cards or on different shelves. address: 20 h (80 h byte) type: read/write format: refer to the following table. tx_ut_wd_alive (0) 1 the phy device at address 0 has responded to polling with an assertion of tatm_clav(3:0) for a period less than wd_time. 0 the phy device at address 0 has not responded to a poll with an assertion of tatm_clav(3:0) for a period longer than wd_time. phy device 0 has expired, therefore drain remaining cells intended for phy device 0 at lowest priority. field (bits) description not used (31:7) write with a 0 to maintain software compatibility with future versions. rx_cell_start_align (6:0) alignment value for the internal rxcellstart signal from the external rx_cell_start signal. (continued) field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 123 7.2.17 rx_queue_engine_test address: 28 h (a0 h byte) type: read/write function: the bits in this register disable individual functions within the queue engine for system debug purposes. ? each instance of the b process (the utopia receive buffering process) performs the vpi/vci map- ping of a new cell from the utopia interface to a receive ccb channel number. ? the u process (the utopia enqueue process) uses the receive ccb channel number from the b process and peforms the cell enqueue function, including any congestion control. ? the s process (the receive switch fabric cell sending process) fetches a cell for switch fabric dequeue. ? the p process (the receive switch fabric acknowledge post-processing process) analyzes the ack response from the previous cell transmission. reset value: 0 format: refer to the following table. field (bits) description reserved (31:27) write with 0 to maintain future software compatibility. rx_4_rr_ptrs (26) 1 use 4 separate sets of round robin pointers, one set for each s process. use this to achieve more predictable multicast performance when the bit separate_out_mc is set. this also allows more effective timeslot entries to be used when separate_out_mc is cleared. this setting can only be used when al_ram_config is not equal to 0. 0 use 1 set of round robin pointers. rx_stats (25) 1 enable the storage of rx_ch_stats in the abram 0 disable the storage of rx_ch_stats in the abram. use this setting when only 64k x 16 of memory is present or if the rx_ch_stats are not needed. rx_long_svc_tbl (24) 1 use 511 entry long rx_service_table. this allows finer control of the bandwidth. this setting can only be used when al_ram_config is not equal to 0. 0 use 127 entry long rx_service_table. reserved (23) write with 0 to maintain future software compatibility. rx_scg_enable (22) 1 enforce the service class group congestion limits configured in rx_lwrxx_max_qd and rx_lwrxx_exp_cong_qd. note: when this feature is enabled, the maximum queue depth for any of the three service class groups is 31k cells. 0 ignore the configured scg congestion limits rx_red_enable (21) 1 enable random early packet discard function. the rx_xxx_exp_cong_qd that is used for each of the ch, sc, scg, and dir settings is randomly chosen to be the user configured one or the value one codepoint below the configured value. 0 red disabled
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 124 rx_clp_before_epd_enabl e (20) 1 enable clp before epd dropping. when this feature is enabled, clp=1 cells are dropped at the queue depth defined by the appropriate the code- point one below that defined in rx_xxx_exp_cong_qd triggering ptd (packet tail dropping). clp=0 cells are considered for dropping by the epd algorithm at the queue depth defined by rx_xxx_exp_cong_qd. 0 disable clp before epd dropping. rx_hysteresis_disable (19) 1 disable rx dir, scg, and sc congestion hyteresis. this setting declares that congestion is relieved when the queue depth drops below the queue depth defined by the appropriate rx_xxx_exp_cong_qd. this setting might achieve higher throughput in cases where the incom- ing traffic characteristics are less bursty. 0 enable rx dir, scg, and sc congestion hysteresis. this setting declares that congestion is relieved when the queue depth drops below the queue depth defined by the appropriate the codepoint one below that defined in rx_xxx_exp_cong_qd. this is a more robust setting which forces the switch to make the most of each dropping event at the expense of access to cell buffers in the steady state. field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 125 rx_alternate_encode (18) 1 enable rx, scg, and sc alternate congestion encoding. this set of val- ues of the rx_xxx_exp_max_qd and rx_xxx_exp_cong_qd defines many of the codepoints with higher values. this increases the resolution of the congestion limits where they are used most of the time. the coding is: 1111- 31k+1 (31745) 1110 - 24k+1 1101 - 16k+1 1100 - 12k+1 1011 - 8k+1 1010 - 6k+1 1001 - 4k+1 1000 - 3k+1 0111 - 2k+1 0110 - 1.5k+1 0101 - 1k+1 0100 - 769 0011 - 513 0010 - 257 0001 - 9 0000 - 0 0 disable the rx, scg, and sc alternate encoding. this setting uses the original set of values which are approximately 2**n. the coding is: 1111- 31k+1 (31745) 1110 - 16k+1 1101 - 8k+1 1100 - 4k+1 1011 - 2k+1 1010 - 1k+1 1001 - 513 1000 - 257 0111 - 129 0110 - 65 0101 - 33 0100 - 15 0011 - 9 0010 - 5 0001 - 3 0000 - 0 rx_ch_hysteresis_disable (17) 1 disable rx_ch congestion hyteresis. this setting declares that conges- tion is relieved when the queue depth drops below the queue depth defined by the appropriate rx_xxx_exp_cong_qd. this setting might achieve higher throughput in cases where the incoming traffic characteristics are less bursty. 0 enable rx_ch congestion hysteresis. this setting declares that conges- tion is relieved when the queue depth drops below the queue depth defined by the appropriate the codepoint one below that defined in rx_xxx_exp_cong_qd. this is a more robust setting which forces the switch to make the most of each dropping event at the expense of access to cell buffers in the steady state. field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 126 rx_ch_alternate_encode (16) 1 enable rx_ch alternate congestion encoding. this set of values of the rx_ch_exp_max_qd and rx_ch_exp_cong_qd defines many of the codepoints with higher values. this increases the resolution of the congestion limits where they are used most of the time. the table is shown in the text for rx_alternate_encode. 0 disable rx_ch alternate encoding. this setting uses the original set of values which are approximately 2**n. the table is shown in the text for rx_alternate_encode. disable_p4 (15) 1 disable the 4th instance of the p process. the p process updates the data structures with the results of crossing the switch fabric. p4 works as a pair with s4. 0 enable this process. disable_p3 (14) 1 disable the 3rd instance of the p process. p3 works as a pair with s3. 0 enable this process. disable_p2 (13) 1 disable the 2nd instance of the p process. p2 works as a pair with s2. 0 enable this process. disable_p1 (12) 1 disable the 1st instance of the p process. p1 works as a pair with s1. 0 enable this process. disable_s4 (11) 1 disable the 4th instance of the s process. the s process selects the cells to be sent to the switch fabric. when disable_randomization=1, s4 is associated with switch fabric port 3. 0 enable this process. disable_s3 (10) 1 disable the 3rd instance of the s process.when disable_randomization=1, s3 is associated with switch fabric port 2. 0 enable this process. disable_s2 (9) 1 disable the 2nd instance of the s process. when disable_randomization=1, s2 is associated with switch fabric port 1. 0 enable this process. disable_s1 (8) 1 disable the 1st instance of the s process. when disable_randomization=1, s1 is associated with switch fabric port 0. 0 enable this process. drop_all_rx_cells (7) 1 drop all cells received in the rx direction. 0 normal operation. disable_u3 (6) 1 disable the 3rd instance of the u process. the u process enqueues the cells onto the data structures. 0 enable this process. disable_u2 (5) 1 disable the 2nd instance of the u process. 0 enable this process. disable_u1 (4) 1 disable the 1st instance of the u process. 0 enable this process. field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 127 reserved (3) write with 0 to maintain future software compatibility. disable_b3 (2) 1 disable the 3rd instance of the b process. the b process determines the channel number and enqueues the cell into sdram. b3 works as a pair with u1. 0 enable this process. disable_b2 (1) 1 disable the 2nd instance of the b process. b2 works as a pair with u3. 0 enable this process. disable_b1 (0) 1 disable the 1st instance of the b process. b1 works as a pair with u2. 0 enable this process. field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 128 7.2.18 tx_queue_engine_test address: 29 h (a4 h byte) type: read/write function: the bits in this register disable individual functions within the queue engine for system debug purposes. ? the e process (the transmit switch fabric enqueue process) performs the enqueue function for each cell arrived from the switch process. it determines if a cell is eligible for enqueue (that is, sent or drop) based on current congestion conditions. ? the c process (the update transmit counters process) updates the per-channel statistics. ? the m process (the multicast replication process) performs the multicast leaf replication task. ? the d process (the transmit utopia dequeue process) fetches a cell for transmit utopia transmis- sion. reset value: 0 format: refer to the following table. field (bits) description reserved (31:23) write with a 0 to maintain future software compatibility. tx_scg_enable (22) 1 enforce the service class group congestion limits configured in tx_lwrxx_exp_max_qd and tx_lwrxx_exp_cong_qd. note: when this feature is enabled, the maximum queue depth for any of the three service class groups is 31k cells. 0 ignore the configured scg congestion limits tx_red_enable (21) 1 enable random early packet discard function. the tx_xxx_exp_cong_qd that is used for each of the ch, scq, sc, scg, vo and dir settings is randomly chosen to be the user configured one or the value one codepoint below the configured value. 0 red disabled tx_clp_before_epd_enabl e (20) 1 enable clp before epd dropping. when this feature is enabled, clp=1 cells are dropped at the queue depth defined by the appropriate the code- point one below that defined in tx_xxx_exp_cong_qd triggering ptd (packet tail dropping). clp=0 cells are considered for dropping by the epd algorithm at the queue depth defined by tx_xxx_exp_cong_qd. 0 disable clp before epd dropping. tx_hysteresis_disable (19) 1 disable tx dir, vo, scg, sc and scq congestion hyteresis. this set- ting declares that congestion is relieved when the queue depth drops below the queue depth defined by the appropriate tx_xxx_exp_cong_qd. this setting might achieve higher through- put in cases where the incoming traffic characteristics are less bursty. 0 enable tx dir, vo, scg, sc, and scq congestion hysteresis. this setting declares that congestion is relieved when the queue depth drops below the queue depth defined by the appropriate the codepoint one below that defined in tx_xxx_exp_cong_qd. this is a more robust setting which forces the switch to make the most of each dropping event at the expense of access to cell buffers in the steady state.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 129 tx_alternate_encode (18) 1 enable tx, scg, sc and scq alternate congestion encoding. this set of values of the tx_xxx_exp_max_qd and tx_xxx_exp_cong_qd defines many of the codepoints with higher values. this increases the resolution of the congestion limits where they are used most of the time. the coding is: 1111- 31k+1 (31745) 1110 - 24k+1 1101 - 16k+1 1100 - 12k+1 1011 - 8k+1 1010 - 6k+1 1001 - 4k+1 1000 - 3k+1 0111 - 2k+1 0110 - 1.5k+1 0101 - 1k+1 0100 - 769 0011 - 513 0010 - 257 0001 - 9 0000 - 0 0 disable the tx, sc, scg, and scq alternate encoding. this setting uses the original set of values which are approximately 2**n. the coding is: 1111- 31k+1 (31745) 1110 - 16k+1 1101 - 8k+1 1100 - 4k+1 1011 - 2k+1 1010 - 1k+1 1001 - 513 1000 - 257 0111 - 129 0110 - 65 0101 - 33 0100 - 15 0011 - 9 0010 - 5 0001 - 3 0000 - 0 tx_ch_hysteresis_disable (17) 1 disable tx_ch congestion hyteresis. this setting declares that conges- tion is relieved when the queue depth drops below the queue depth defined by the appropriate tx_xxx_exp_cong_qd. this setting might achieve higher throughput in cases where the incoming traffic characteristics are less bursty. 0 enable tx_ch congestion hysteresis. this setting declares that conges- tion is relieved when the queue depth drops below the queue depth defined by the appropriate the codepoint one below that defined in tx_xxx_exp_cong_qd. this is a more robust setting which forces the switch to make the most of each dropping event at the expense of access to cell buffers in the steady state. field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 130 tx_ch_alternate_encode (16) 1 enable tx_ch alternate congestion encoding. this set of values of the tx_ch_exp_max_qd and tx_ch_exp_cong_qd defines many of the codepoints with higher values. this increases the resolution of the congestion limits where they are used most of the time. the table is shown in the text for rx_alternate_encode. 0 disable tx_ch alternate encoding. this setting uses the original set of values which are approximately 2**n. the table is shown in the text for rx_alternate_encode. tx_disable_bp (15) 1 do not send bp to the switch fabric when the sc mc infifos are almost full. drop cells that are delivered to full queues. this prevents one egress port from congesting the fabric through excessive bp. 0 send bp to the switch fabric when the sc mc infifos are nearly full. this setting allows the egress port to momentarity push back onto the fabric when its infifo becomes full. reserved (13:14) write with a 0 to maintain future software compatibility. drop_all_tx_cells (12) 1 drop all cells received in the tx direction. 0 normal operation. reserved (11) write with 0 to maintain future software compatibility. disable_d3 (10) 1 disable the 3rd instance of the d process. the d process dequeues cells to the utopia. 0 enable this process. disable_d2 (9) 1 disable the 2nd instance of the d process. 0 enable this process. disable_d1 (8) 1 disable the 1st instance of the d process. 0 enable this process. disable_o (7) 1 disable the the o process. the o process updates the tx ch statistics. 0 enable this process. reserved (6) write with 0 to maintain future software compatibility. disable_m2 (5) 1 disable the 2nd instance of the m process. the m process replicates the multicast pointers. 0 enable this process. disable_m1_3 (4) 1 disable the 1st and 3rd instance of the m process. 0 enable this process. disable_e4 (3) 1 disable the 4th instance of the e process. the e process enqueues the cells onto the data structures from the fabric. e4 is associated with switch fabric port 3. 0 enable this process. disable_e3 (2) 1 disable the 3rd instance of the e process. e3 is associated with switch fabric port 2. 0 enable this process. disable_e2 (1) 1 disable the 2nd instance of the e process. e2 is associated with switch fabric port 1. 0 enable this process. field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 131 disable_e1 (0) 1 disable the 1st instance of the e process. e1 is associated with switch fabric port 1. 0 enable this process. field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 132 7. 2. 19. queue engine condition_pres_bits address: 2a h (a8 h byte) read-only. all bits unless specified resets to 0. format: field (bits) description ab_ram_parity_fail (31) 1 the parity on the last ab ram read was not odd. 0 the parity on the last ab ram read was odd. sf_fabric_not_sync_fail (30) 1 the rx_cell_start pulse did not arrive at exactly 118 sf_clk clock interval. the fabric interface is out of sync because of this condi- tion. 0 the rx_cell_start pulse is occuring at exactly 118 sf_clk clocks interval. the fabric interface is in sync. not used (29:27) driven with a 0. ch_unused_vci_set (26) 1 a cell was received with a vpi with a vpi with vcc_entry=1 and a vci bit set great than that defined by the value of vci_bits for that vpi. 0 the cell that was just received did not have an unused vci bit set. qe_tx_scg_fail (25) 1 an illegal state is present in one of the three tx service class group counters. this check asserts that whenever there are no cells in the lower 12 services classes, there must also be no cells in the lower 4 service classes. this is a non-recoverable state for the device. the device should be reset and reinitialized. 0 the tx service class group counters are currently in a legal state. qe_rx_scg_fail (24) 1 an illegal state is present in one of the three rx service class group counters. this check asserts that whenever there are no cells in the lower 48 services classes, there must also be no cells in the lower 16 service classes. this is a non-recoverable state for the device. the device should be reset and reinitialized. 0 the rx service class group counters are currently in a legal state. qe_tx_lower12_scg_qd_ne g (23) 1 the tx lower12 service class group queue depth is negative. this is a non-recoverable state for the device. the device should be reset and reinitialized. 0 the tx lower12 service class group queue depth is non-negative. qe_tx_lower8_scg_qd_neg (22) 1 the tx lower8 service class group queue depth is negative. this is a non-recoverable state for the device. the device should be reset and reinitialized. 0 the tx lower8 service class group queue depth is non-negative. qe_tx_lower4_scg_qd_neg (21) 1 the tx lower4 service class group queue depth is negative. this is a non-recoverable state for the device. the device should be reset and reinitialized. 0 the tx lower4 service class group queue depth is non-negative. qe_tx_dir_qd_neg (20) 1 the tx direction queue depth is negative. this is a non-recoverable state for the device. the device should be reset and reinitialized. 0 the tx direction queue depth is non-negative.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 133 qe_rx_lower48_scg_qd_ne g (19) 1 the rx lower48 service class group queue depth is negative. this is a non-recoverable state for the device. the device should be reset and reinitialized. 0 the rx lower48 service class group queue depth is non-negative. qe_rx_lower32_scg_qd_ne g (18) 1 the rx lower32 service class group queue depth is negative. this is a non-recoverable state for the device. the device should be reset and reinitialized. 0 the rx lower32 service class group queue depth is non-negative. qe_rx_lower16_scg_qd_ne g (17) 1 the rx lower16 service class group queue depth is negative. this is a non-recoverable state for the device. the device should be reset and reinitialized. 0 the rx lower16 service class group queue depth is non-negative. qe_rx_dir_qd_neg (16) 1 the rx direction queue depth is negative. this is a non-recoverable state for the device. the device should be reset and reinitialized. 0 the rx direction queue depth is non-negative. not used (15) driven with a 0 qe_invalid_cstart (14) 1 the internally generated rx cell start did not arrive within 254 sysclks. this is a sign that the seclk is absent or is running too slowly. 0 the internally generated rx cell start arrived within 254 sysclks. qe_rx_seq_fail (13) 1 an illegal state is present in the rx sequencing state machine. this is likely a non-recoverable state for the device. the device should be reset and reinitialized. 0 the rx sequencing state machine is currently in a legal state. qe_tx_ch_qd_neg (12) 1 a tx channel queue depth is negative. this is a non-recoverable state for the device. the device should be reset and reinitialized. 0 a tx channel queue depth is non-negative. qe_tx_scq_qd_neg (11) 1 a tx service class queue, queue depth is negative. this is a non- recoverable state for the device. the device should be reset and reinitial- ized. 0 a tx service class queue, queue depth is non-negative. qe_tx_sc_qd_neg (10) 1 a tx service class queue depth is negative. this is a non-recoverable state for the device. the device should be reset and reinitialized. 0 a tx service class queue depth is non-negative. qe_tx_vo_qd_neg (9) 1 a tx virtual output queue depth is negative. this is a non-recoverable state for the device. the device should be reset and reinitialized. 0 a tx virtual output queue depth is non-negative. qe_rx_ch_qd_neg (8) 1 a rx channel queue depth is negative. this is a non-recoverable state for the device. the device should be reset and reinitialized. 0 a rx channel queue depth is non-negative. qe_rx_sc_qd_neg (7) 1 a rx service class queue depth is negative. this is a non-recoverable state for the device. the device should be reset and reinitialized. 0 a rx service class queue depth is non-negative. field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 134 qe_rx_ch_count_neg (6) 1 a rx channel count depth is negative. this is a non-recoverable state for the device. the device should be reset and reinitialized. 0 a rx channel count depth is non-negative. qe_rx_etop_parity (5) 1 the pointer to the top of the rx empty stack has even parity. this is an error if the driver has initialized all of the pointers to be odd. if 64k cell buffers are used, or if the driver did not initialize the pointers to have odd parity by using the msb as a parity bit, this bit may be set. 0 the pointer to the top of the rx empty stack has odd parity. qe_tx_etop_parity (4) 1 the pointer to the top of the tx empty stack has even parity. this is an error if the driver has initialized all of the pointers to be odd. if 64k cell buffers are used, or if the driver did not initialize the pointers to have odd parity by using the msb as a parity bit, this bit may be set. 0 the pointer to the top of the tx empty stack has odd parity. qe_unmapped_vi (3) 1 the rx utopia i/f is delivering a cell from a virtual input that it was not supposed to be polling. 0 .the rx utopia i/f is not delivering a cell from a vi that it was not supposed to be polling. qe_vo_mismatch (2) 1 the tx utopia i/f is asking for a cell from a vo which does not have a cell. this is normal if tx_oc_12c_mode = 1. 0 the tx utopia i/f is not asking for a cell from a vo which does not have a cell. qe_rx_circ_link (1) 1 a circular link is being written to the rx linked list. this non-recover- able state occurs when a link is added to the rx linked list that points to itself. the device should be reset and reinitialized. 0 a circular link is not being written to the rx linked list. qe_tx_circ_link (0) 1 a circular link is being written to the tx linked list. this non-recover- able state occurs when a link is added to the tx linked list that points to itself. the device should be reset and reinitialized. 0 a circular link is not being written to the tx linked list. field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 135 7. 2. 20. queue_engine_condition_latch_bits address: 2b h (ac h byte) read-only - cleared on read. all bits reset to 0 unless specified. format: field (bits) description ab_ram_parity_fail_latch (31) 1 the ab_ram_parity_fail condition occurred since this latch was read 0 the ab_ram_parity_fail condition has not occurred since this latch was read sf_fabric_not_sync_latch (30) 1 the rx_cell_start pulse did not arrive at exactly 118 sf_clk clock interval. the fabric interface is out of sync because of this condition. 0 the rx_cell_start pulse is occuring at exactly 118 sf_clk clocks interval. the fabric interface is in sync. not used (29:27) driven with a 0. ch_unused_vci_set_latch (26) 1 the ch_unused_vci_set condition occurred since this latch was read 0 the ch_unused_vci_set condition has not occurred since this latch was read qe_tx_scg_fail_latch (25) 1 the qe_tx_scg_fail condition occurred since this latch was read 0 the qe_tx_scg_fail condition has not occurred since this latch was read qe_rx_scg_fail_latch (24) 1 the qe_rx_scg_fail condition occurred since this latch was read 0 the qe_rx_scg_fail condition has not occurred since this latch was read qe_tx_lower12_scg_qd_neg_ latch (23) 1 the qe_tx_lower12_scg_qd_neg condition occurred since this latch was read 0 the qe_tx_lower12_scg_qd_neg condition has not occurred since this latch was read qe_tx_lower8_scg_qd_neg_l atch (22) 1 the qe_tx_lower8_scg_qd_neg condition occurred since this latch was read 0 the qe_tx_lower8_scg_qd_neg condition has not occurred since this latch was read qe_tx_lower4_scg_qd_neg_l atch (21) 1 the qe_tx_lower4_scg_qd_neg condition occurred since this latch was read 0 the qe_tx_lower4_scg_qd_neg condition has not occurred since this latch was read qe_tx_dir_qd_neg_latch (20) 1 the qe_tx_dir_qd_neg condition occurred since this latch was read 0 the qe_tx_dir_qd_neg condition has not occurred since this latch was read
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 136 qe_rx_lower48_scg_qd_neg_ latch (19) 1 the qe_rx_lower48_scg_qd_neg condition occurred since this latch was read 0 the qe_rx_lower48_scg_qd_neg condition has not occurred since this latch was read qe_rx_lower32_scg_qd_neg_ latch (18) 1 the qe_rx_lower32_scg_qd_neg condition occurred since this latch was read 0 the qe_rx_lower32_scg_qd_neg condition has not occurred since this latch was read qe_rx_lower16_scg_qd_neg_ latch (17) 1 the qe_rx_lower16_scg_qd_neg condition occurred since this latch was read 0 the qe_rx_lower16_scg_qd_neg condition has not occurred since this latch was read qe_rx_dir_qd_neg_latch (16) 1 the qe_rx_dir_qd_neg condition occurred since this latch was read 0 the qe_rx_dir_qd_neg condition has not occurred since this latch was read not used (15) driven with a 0. qe_invalid_cstart_latch (14) 1 the qe_invalid_cstart condition occurred since this latch was read 0 the qe_invalid_cstart condition has not occurred since this latch was read qe_rx_seq_fail_latch (13) 1 the qe_rx_seq_fail condition has occurred since this latch was read. 0 the qe_rx_seq_fail condition has not occurred since this latch was read. qe_tx_ch_qd_neg_latch (12) 1 the qe_tx_ch_qd_neg condition has occurred since this latch was read. 0 the qe_tx_ch_qd_neg condition has not occurred since this latch was read. qe_tx_scq_qd_neg_latch (11) 1 the qe_tx_scq_qd_neg condition has occurred since this latch was read. 0 the qe_tx_scq_qd_neg condition has not occurred since this latch was read. qe_tx_sc_qd_neg_latch (10) 1 the qe_tx_sc_qd_neg condition has occurred since this latch was read. 0 the qe_tx_sc_qd_neg condition has not occurred since this latch was read. qe_tx_vo_qd_neg_latch (9) 1 the qe_tx_vo_qd_neg condition has occurred since this latch was read. 0 the qe_tx_vo_qd_neg condition has not occurred since this latch was read. qe_rx_ch_qd_neg_latch (8) 1 the qe_rx_ch_qd_neg condition has occurred since this latch was read. 0 the qe_rx_ch_qd_neg condition has not occurred since this latch was read. field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 137 qe_rx_sc_qd_neg_latch (7) 1 the qe_rx_sc_qd_neg condition has occurred since this latch was read. 0 the qe_rx_sc_qd_neg condition has not occurred since this latch was read. qe_rx_ch_count_neg_latch (6) 1 the qe_rx_ch_count_neg condition has occurred since this latch was read. 0 the qe_rx_ch_count_neg condition has not occurred since this latch was read. qe_rx_etop_parity_latch (5) 1 the qe_rx_etop_parity condition has occurred since this latch was read. if 64k cell buffers are used, or if the driver did not initial- ize the pointers to have odd parity by using the msb as a parity bit, this bit may be set. 0 the qe_rx_etop_parity condition has not occurred since this latch was read. qe_tx_etop_parity_latch (4) 1 the qe_tx_etop_parity condition has occurred since this latch was read. if 64k cell buffers are used, or if the driver did not initial- ize the pointers to have odd parity by using the msb as a parity bit, this bit may be set. 0 the qe_tx_etop_parity condition has not occurred since this latch was read. qe_unmapped_vi_latch (3) 1 the qe_unmapped_vi condition has occurred since this latch was read. 0 the qe_unmapped_vi condition has not occurred since this latch was read. qe_vo_mismatch_latch (2) 1 the qe_vo_mismatch condition has occurred since this latch was read. this is normal if tx_oc_12c_mode = 1. 0 the qe_vo_mismatch condition has not occurred since this latch was read. qe_rx_circ_link_latch (1) 1 the qe_rx_circ_link condition has occurred since this latch was read. 0 the qe_rx_circ_link condition has not occurred since this latch was read. qe_tx_circ_link_latch (0) 1 the qe_tx_circ_link condition has occurred since this latch was read. 0 the qe_tx_circ_link condition has not occurred since this latch was read. field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 138 7. 2. 21. queue_engine_int_mask address: 2c h (b0 h byte) read/write function: the following mask_ bits disable the generation of an interrupt through the intr pin. they do not, however, affect the operation of the associated interrupt or status bits. reset value:1 format: field (bits) description mask_ab_ram_parity_fail (31) 1 mask the ab_ram_parity_fail interrupt. 0 enable this interrupt. mask_sf_fabric_not_sync _fail (30) 1 mask the the rx_cell_start pulse not occuring at exactly 118 sf_clk clock interval interrupt 0 enable this interrupt. not used (29:27) write with a 1 to maintain future software compatibility. mask_ch_unused_vci_set (26) 1 mask the ch_unused_vci_set interrupt. 0 enable this interrupt. mask_qe_tx_scg_fail (25) 1 mask the qe_tx_scg_fail interrupt. 0 enable this interrupt. mask_qe_rx_scg_fail (24) 1 mask the qe_rx_scg_fail interrupt. 0 enable this interrupt. mask_qe_tx_lower12_scg_ qd_neg (23) 1 mask the qe_tx_lower12_scg_qd_neg interrupt. 0 enable this interrupt. mask_qe_tx_lower8_scg_ qd_neg (22) 1 mask the qe_tx_lower8_scg_qd_neg interrupt. 0 enable this interrupt. mask_qe_tx_lower4_scg_ qd_neg (21) 1 mask the qe_tx_lower4_scg_qd_neg interrupt. 0 enable this interrupt. mask_qe_tx_dir_qd_neg (20) 1 mask the qe_tx_dir_qd_neg interrupt. 0 enable this interrupt. mask_qe_rx_lower48_scg_ qd_neg (19) 1 mask the qe_rx_lower48_scg_qd_neg interrupt. 0 enable this interrupt. mask_qe_rx_lower32_scg_ qd_neg (18) 1 mask the qe_rx_lower32_scg_qd_neg interrupt. 0 enable this interrupt. mask_qe_rx_lower16_scg_ qd_neg (17) 1 mask the qe_rx_lower16_scg_qd_neg interrupt. 0 enable this interrupt. mask_qe_rx_dir_qd_neg (16) 1 mask the qe_rx_dir_qd_neg interrupt. 0 enable this interrupt.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 139 not used (15) write with a 1 to maintain future software compatibility. mask_qe_invalid_cstart (14) 1 mask the qe_invalid_cstart interrupt. 0 enable this interrupt. mask_qe_rx_seq_fail (13) 1 mask the qe_rx_seq_fail interrupt. 0 enable this interrupt. mask_qe_tx_ch_qd_neg (12) 1 mask the qe_tx_ch_qd_neg interrupt. 0 enable this interrupt. mask_qe_tx_scq_qd_neg (11) 1 mask the qe_tx_scq_qd_neg interrupt. 0 enable this interrupt. mask_qe_tx_sc_qd_neg (10) 1 mask the qe_tx_sc_qd_neg interrupt. 0 enable this interrupt. mask_qe_tx_vo_qd_neg (9) 1 mask the qe_tx_vo_qd_neg interrupt. 0 enable this interrupt. mask_qe_rx_ch_qd_neg (8) 1 mask the qe_rx_ch_qd_neg interrupt. 0 enable this interrupt. mask_qe_rx_sc_qd_neg (7) 1 mask the qe_rx_sc_qd_neg interrupt. 0 enable this interrupt. mask_qe_rx_ch_count_ne g (6) 1 mask the qe_rx_ch_count_neg interrupt 0 enable this interrupt. mask_qe_rx_etop_parity (5) 1 mask the qe_rx_etop_parity interrupt 0 enable this interrupt. mask_qe_tx_etop_parity (4) 1 mask the qe_rx_etop_parity interrupt 0 enable this interrupt. mask_qe_unmapped_vi (3) 1 mask the qe_unmapped_vi interrupt. 0 enable this interrupt. mask_qe_vo_mismatch (2) 1 mask the qe_vo_mismatch interrupt. 0 enable this interrupt. mask_qe_rx_circ_link (1) 1 mask the qe_rx_circ_link interrupt. 0 enable this interrupt. mask_qe_tx_circ_link (0) 1 mask the qe_tx_circ_link interrupt. 0 enable this interrupt. field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 140 7.2.22 rx_dir_config the rx_dir_exp_econg_qd bit in this register sets the congestion threshold for the receive direction. when the number of free cell buffers falls below this threshold, the configured conges- tion management actions are taken. a low number sets this threshold to a high number of used cell buffers. address: 1f0000 h (7c0000 h byte) type: read/write format: refer to the following table. 7.2.23 rx_dir_state (internal structure) address: 1f0001 h (7c0004 h byte) type: read/write C write only during sw_reset (refer to sw_reset on page 101 ). do not update this register. format: refer to the following table. field (bits) description not used (31:16) write with a 0 to maintain software compatibility with future versions. reserved (15:12) write with a 3 h . rx_dir_exp_econg_qd (11:8) exponent of the congested queue depth (this is, the number of empty cell buffers below which the device will enter the empty congestion state). initialize to the proper setting. the congestion state is entered when the number of free buffers drops below this thresh- old, and the congestion state is exited when the number of free buffers exceeds twice this threshold. not used (7:0) write with a 0 to maintain software compatibility with future versions. field (bits) description not used (31:18) write with a 0 to maintain software compatibility with future versions. reserved (17) initialize to 0 at initial setup. software modifications to this location after setup may cause incorrect operation. rx_dir_cong_state (16) congestion state. initialize to 0. rx_dir_e_cur_qd (15:0) current count of empty cells in the receive direction. initialize to the number of cells setting. note: the number of buffers is limited to the physical number of buffers minus three.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 141 7.2.24 tx_dir_config address: 1f0008 h (7c0020 h byte) type: read/write format: refer to the following table. 7.2.25 tx_dir_state (internal structure) address: 1f0009 h (7c0024 h byte) type: read/write C write only during sw_reset (refer to sw_reset on page 101 ). do not update this register. format: refer to the following table. field (bits) description not used (31:16) write with a 0 to maintain software compatibility with future versions. reserved (15:12) write with a 3. tx_dir_exp_cong_qd (11:8) exponent of the congested queue depth (this is the number of empty cell buffers below which the device will enter the empty congestion state). initialize to the proper setting. the congestion state is entered when the number of free buffers drops below this thresh- old, and the congestion state is exited when the number of free buffers exceeds twice this threshold. note: this field determines the number of empty buffers rather than the number of full buffers. not used (7:0) write with a 0 to maintain software compatibility with future versions. field (bits) description not used (31:18) write with a 0 to maintain software compatibility with future versions. reserved (17) initialize to 0 at initial setup. software modifications to this location after setup may cause incorrect operation. tx_dir_e_cong_state (16) current empty congestion state. initialize to 0. this bit is read-only. tx_dir_e_cur_qd (15:0) current count of empty cells in the transmit direction. initialize to the number of cells setting. note: the number of buffers is limited to the physical number of buffers minus two.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 142 7.2.26 rx_sent_cells address: 1f0010 h (7c0040 h byte) type: read-only function: counts the number of cells accepted by the receive direction. reset value:0 format: refer to the following table. 7.2.27 rx_dropped_cells address: 1f0011 h (7c0044 h byte) type: read-only function: counts the number of cells dropped by the receive direction. reset value: 0 format: refer to the following table. 7.2.28 tx_sent_cells address: 1f0012 h (7c0048 h byte) type: read-only function: counts the number of cells accepted (queued) by the transmit direction. reset value: 0 format: refer to the following table. field (bits) description not used (31:24) write with a 1 to maintain future software compatibility. rx_sent_cells (23:0) 24-bit rollover counter of the number of cells accepted by the receive direction. this counter is reset to 0 when sw_reset = 1 or hw_reset = 1 (refer to sw_reset and hw_reset on page 101 ). field (bits) description not used (31:24) write with a 1 to maintain future software compatibility. rx_dropped_cells (23:0) 24-bit rollover counter of the number of cells dropped by the receive direction. this counter is reset to 0 when sw_reset = 1 or hw_reset = 1 (refer to sw_reset and hw_reset on page 101 ). field (bits) description not used (31:24) write with a 1 to maintain future software compatibility. tx_sent_cells (23:0) 24-bit rollover counter of the number of cells accepted by the transmit direction. this counter is reset to 0 when sw_reset = 1 or hw_reset = 1 (refer to sw_reset and hw_reset on page 101 ).
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 143 7.2.29 tx_dropped_cells address: 1f0013 h (7c004c h byte) type: read-only function: counts the number of cells dropped by the transmit direction. reset value: 0 format: refer to the following table. field (bits) description not used (31:24) write with a 1 to maintain future software compatibility. tx_dropped_cells (23:0) 24-bit rollover counter of the number of cells dropped by the transmit direction. this counter is reset to 0 when sw_reset = 1 or hw_reset = 1 (refer to sw_reset and hw_reset on page 101 ).
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 144 7. 2. 30. rx_lower16_scg_config address: 1f0014 h (7c0050 h ) read/write function: congestion configuration register for lower 16 (sc 24-31 and sc 56-63) service class group reset value:0 format: 7. 2. 31. rx_lower16_scg_state (internal state) address: 1f0015 h (7c0054 h ) read/write function: queue state for lower 16 (sc 24-31 and sc 56-63) service class group reset value:0 format: field (bits) description not used (31:16) write with a 0 to maintain future software compatibility. rx_lwr16_exp_max_qd (15:12) maximum qd (exponent or alternate) for service class group 24-31 and 56-63. this limit is enforced if rx_scg_enable=1. rx_lwr16_exp_cong_qd (11:8) congestion qd (exponent or alternate) for service class group 24-31 and 56-63. this limit is enforced if rx_scg_enable=1. not used (7:0) write with a 0 to maintain future software compatibility. field (bits) description not used (31:20) write with a 0 to maintain future software compatibility. rx_lwr16_maxed (19) this scg is currently in max congestion. resets to 0. read-only. rx_lwr16_decr_cong (18) this queue depth for this service class group is currently larger than the queue depth defined by one codepoint less than rx_lwr16_cong_qd. resets to 0. read- only. rx_lwr16_def_cong (17) this queue depth for this service class group is currently larger than the queue depth defined by rx_lwr16_cong_qd. resets to 0. read-only. rx_lwr16_congested (16) this service class group is currently in congestion as defined by rx_lwr16_cong_qd, rx_hysteresis_disable, and rx_alternate_encode. resets to 0. read-only. reserved (15) write with 0 each time sw_reset is asserted to maintain future sw compatibility. rx_lwr16_data (14:0) current queue depth for this scg. initialize to 0000 each time sw_reset is asserted to maintain software compaitibility. resets to 0000.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 145 7. 2. 32. rx_lower32_scg_config address: 1f0016 h (7c0058 h ) read/write function: congestion configuration register for lower 32 (sc 16-31 and sc 48-63) service class group reset value:0 format: 7. 2. 33. rx_lower32_scg_state (internal state) address: 1f0017 h (7c005c h ) read/write: function: queue state for lower 32 (sc 16-31 and sc 48-63) service class group reset value:0 format: field (bits) description not used (31:16) write with a 0 to maintain future software compatibility. rx_lwr32_exp_max_qd (15:12) maximum qd (exponent or alternate) for the cells in service class groups 16-31 and 48-63. this limit is enforced if rx_scg_enable=1. rx_lwr32_exp_cong_qd (11:8) congestion qd (exponent or alternate) for the cells in service class groups 16-31 and 48-63. this limit is enforced if rx_scg_enable=1. not used (7:0) write with a 0 to maintain future software compatibility. field (bits) description not used (31:20) write with a 0 to maintain future software compatibility. rx_lwr32_maxed (19) this scg is currently in max congestion. resets to 0. read-only. rx_lwr32_decr_cong (18) this queue depth for this service class group is currently larger than the queue depth defined by one codepoint less than rx_lwr32_cong_qd. resets to 0. read- only. rx_lwr32_def_cong (17) this queue depth for this service class group is currently larger than the queue depth defined by rx_lwr32_cong_qd. resets to 0. read-only. rx_lwr32_congested (16) this service class group is currently in congestion as defined by rx_lwr32_cong_qd, rx_hysteresis_disable, and rx_alternate_encode. resets to 0. read-only. reserved (15) write with 0 each time sw_reset is asserted to maintain future sw compatibility. rx_lwr32_data (14:0) current queue depth for this scg. initialize to 0000 each time sw_reset is asserted to maintain software compaitibility. resets to 0000.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 146 7. 2. 34. rx_lower48_scg_config address: 1f0018 h (7c0060 h ) read/write function: congestion configuration register for lower 48 (sc 8-31 and sc 40-63) service class group reset value:0 format: 7. 2. 35. rx_lower48_scg_state (internal state) address: 1f0019 h (7c0064 h ) read/write function: queue state for lower 48 (sc 8-31 and sc 40-63) service class group reset value:0 format: field (bits) description not used (31:16) write with a 0 to maintain future software compatibility. rx_lwr48_exp_max_qd (15:12) maximum qd (exponent or alternate) for service class group 8-31 and 40-63. this limit is enforced if rx_scg_enable=1. rx_lwr48_exp_cong_qd (11:8) congestion qd (exponent or alternate) for service class group 8-31 and 40-63. this limit is enforced if rx_scg_enable=1. not used (7:0) write with a 0 to maintain future software compatibility. field (bits) description not used (31:20) write with a 0 to maintain future software compatibility. rx_lwr48_maxed (19) this scg is currently in max congestion. resets to 0. read-only. rx_lwr48_decr_cong (18) this queue depth for this service class group is currently larger than the queue depth defined by one codepoint less than rx_lwr48_cong_qd. resets to 0. read- only. rx_lwr48_def_cong (17) this queue depth for this service class group is currently larger than the queue depth defined by rx_lwr48_cong_qd. resets to 0. read-only. rx_lwr48_congested (16) this service class group is currently in congestion as defined by rx_lwr48_cong_qd, rx_hysteresis_disable, and rx_alternate_encode. resets to 0. read-only. reserved (15) write with 0 each time sw_reset is asserted to maintain future sw compatibility. rx_lwr48_data (14:0) current queue depth for this scg. initialize to 0000 each time sw_reset is asserted to maintain software compaitibility. resets to 0000.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 147 7. 2. 36. tx_lower4_scg_config address: 1f001a h (7c0068 h ) read/write function: congestion configuration register for lower 4 (sc 6-7 and 14-15) service class group reset value:0 format: 7. 2. 37. tx_lower4_scg_state (internal state) address: 1f001b h (7c006c h ) read/write function: queue state for lower 4 (sc 6-7 and 14-15) service class group reset value:0 format: field (bits) description not used (31:16) write with a 0 to maintain future software compatibility. tx_lwr4_exp_max_qd (15:12) maximum qd (exponent or alternate) for service class group 6-7 and 14-15. this limit is enforced if tx_scg_enable=1. tx_lwr4_exp_cong_qd (11:8) congestion qd (exponent or alternate) for service class group 6-7 and 14-15. this limit is enforced if tx_scg_enable=1. not used (7:0) write with a 0 to maintain future software compatibility. field (bits) description not used (31:20) write with a 0 to maintain future software compatibility. tx_lwr4_maxed (19) this scg is currently in max congestion. resets to 0. read-only. tx_lwr4_decr_cong (18) this queue depth for this service class group is currently larger than the queue depth defined by one codepoint less than tx_lwr4_cong_qd. resets to 0. read- only. tx_lwr4_def_cong (17) this queue depth for this service class group is currently larger than the queue depth defined by tx_lwr4_cong_qd. resets to 0. read-only. tx_lwr4_congested (16) this service class group is currently in congestion as defined by tx_lwr4_cong_qd, tx_hysteresis_disable, and tx_alternate_encode. resets to 0. read-only. reserved (15) write with 0 each time sw_reset is asserted to maintain future sw compatibility. tx_lwr4_data (14:0) current queue depth for this scg. initialize to 0000 each time sw_reset is asserted to maintain software compaitibility. resets to 0000.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 148 7. 2. 38. tx_lower8_scg_config address: 1f001c h (7c0070 h ) read/write function: congestion configuration register for lower 8 (sc 4-7 and 12-15) service class group reset value:0 format: 7. 2. 39. tx_lower8_scg_state (internal state) address: 1f001d h (7c0074 h ) read/write function: queue state for lower 8 (sc 6-7 and 14-15) service class group reset value:0 format: field (bits) description not used (31:16) write with a 0 to maintain future software compatibility. tx_lwr8_exp_max_qd (15:12) maximum qd (exponent or alternate) for service class group 4-7 and 12-15. this limit is enforced if tx_scg_enable=1. tx_lwr8_exp_cong_qd (11:8) congestion qd (exponent or alternate) for service class group 4-7 and 12-15. this limit is enforced if tx_scg_enable=1. not used (7:0) write with a 0 to maintain future software compatibility. field (bits) description not used (31:20) write with a 0 to maintain future software compatibility. tx_lwr8_maxed (19) this scg is currently in max congestion. resets to 0. read-only. tx_lwr8_decr_cong (18) this queue depth for this service class group is currently larger than the queue depth defined by one codepoint less than tx_lwr8_cong_qd. resets to 0. read- only. tx_lwr8_def_cong (17) this queue depth for this service class group is currently larger than the queue depth defined by tx_lwr8_cong_qd. resets to 0. read-only. tx_lwr8_congested (16) this service class group is currently in congestion as defined by tx_lwr8_cong_qd, tx_hysteresis_disable, and tx_alternate_encode. resets to 0. read-only. reserved (15) write with 0 each time sw_reset is asserted to maintain future sw compatibility. tx_lwr8_data (14:0) current queue depth for this scg. initialize to 0000 each time sw_reset is asserted to maintain software compaitibility. resets to 0000.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 149 7. 2. 40. tx_lower12_scg_config address: 1f001e h (7c0078 h ) read/write function: congestion configuration register for lower 12 (sc 2-7 and 10-15) service class group reset value:0 format: 7. 2. 41. tx_lower12_scg_state (internal state) address: 1f001f h (7c007c h ) read/write function: queue state for lower 12 (sc 2-7 and 10-15) service class group reset value:0 format: field (bits) description not used (31:16) write with a 0 to maintain future software compatibility. tx_lwr8_exp_max_qd (15:12) maximum qd (exponent or alternate) for service class group 2-7 and 10-15. this limit is enforced if tx_scg_enable=1. tx_lwr8_exp_cong_qd (11:8) congestion qd (exponent or alternate) for service class group 2-7 and 10-15. this limit is enforced if tx_scg_enable=1. not used (7:0) write with a 0 to maintain future software compatibility. field (bits) description not used (31:20) write with a 0 to maintain future software compatibility. tx_lwr12_maxed (19) this scg is currently in max congestion. resets to 0. read-only. tx_lwr12_decr_cong (18) this queue depth for this service class group is currently larger than the queue depth defined by one codepoint less than tx_lwr12_cong_qd. resets to 0. read- only. tx_lwr12_def_cong (17) this queue depth for this service class group is currently larger than the queue depth defined by tx_lwr12_cong_qd. resets to 0. read-only. tx_lwr12_congested (16) this service class group is currently in congestion as defined by tx_lwr12_cong_qd, tx_hysteresis_disable, and tx_alternate_encode. resets to 0. read-only. reserved (15) write with 0 each time sw_reset is asserted to maintain future sw compatibility. tx_lwr12_data (14:0) current queue depth for this scg. initialize to 0000 each time sw_reset is asserted to maintain software compaitibility. resets to 0000.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 150 8 internal ram memory map 8.1 internal ram summary the internal ram contains the following ram regions: ? transmit service class ram (tsc_ram) 2560 16 ? receive service class ram (rsc_ram) 388 16 ? virtual output control ram (vo_ram) 256 16 ? receive switch fabric control ram (rsf_control_ram) 40 32 ? transmit switch fabric control ram (tsf_control_ram) 12 28 ? receive utopia ram (ru_ram) 64 32 (4 cell buffers) ? transmit utopia ram (tu_ram) 48 32 (3 cell buffers) ? receive switch element ram (rs_ram) 128 32 (8 cell buffers) ? transmit switch element ram (ts_ram) 192 32 (12 cell buffers) ? queue engine registers. table 25. internal ram summary byte address long address name description 400000- 4027fc h 100000-1009ff h transmit service class ram (tsc_ram) contains the transmit sc queue control block. 440000-44060c h 110000-110183 h receive service class ram (rsc_ram) contains the receive sc ram. 480000- 4803fc h 120000-1200ff h virtual output control ram (vo_ram) contains the control tables for the vos and the direction control. 4c0000- 4c00a0 h 130000-130028 h receive switch fabric con- trol ram (rsf_control_ram) contains the control table for cell buffers in transmission at the receive switch fabric interfaces. 500000-50002c h 140000-14000b h transmit switch fabric con- trol ram (tsf_control_ram) contains the control table for cell buffers in transmission at the transmit switch fabric interfaces. 540000- 5400fc h 150000-15003f h test access to the receive utopia ram (ru_ram) contains the cell buffers for cells headed from the utopia interface. 580000-5800c0 h 160000-160030 h test access to the transmit utopia ram (tu_ram) contains the cell buffers for cells headed toward the uto- pia interface. 5c0000- 5c01fc h 170000-17007f h test access to the receive switch element ram (rs_ram) contains the cell buffers for cells headed toward the switch fabric. 600000- 6002fc h 180000-1800bf h test access to the transmit switch element ram (ts_ram) contains the cell buffers for cells coming from the switch fabric. 7c0000- 7c004c h 1f0000-1f0013 h queue engine registers for information, refer to sections queue engine condition_pres_bits on page 132 , rx_dir_state (internal structure) on page 140 , tx_dir_config on page 141 , and tx_dir_state (internal structure) on page 141 .
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 151 notes: ? all bits marked reserved must be initialized to 0 (unless otherwise indicated) at initial setup. soft- ware modifications to these locations after setup may cause incorrect operation. ? all read/write bits marked not used must be written with the value 0 to maintain software compatibil- ity with future versions. ? most read-only bits marked not used are driven with a 0; however, some may have an unpredictable value on reads. therefore, all read-only bits marked not used should be masked by the software on reads to maintain compatibility with future versions. ? ram is not present in bit locations marked not present. 8.2 transmit service class ram (tsc_ram) summary the tsc_ram contains the transmit service class queue (tx scq) control block. figure 67 shows a memory map of the tsc_ram. figure 67. transmit service class ram (tsc_ram) memory map tx scq control block(0) 100003 h 100004 h vo = 0 sc = 0 d0 d15 tx scq control block(1) vo = 0 sc = 1 100007 h tx scq control block(495) vo=30 sc=15 not used 100000 h 1007b8 h 1007bf h 1007c0 h 1009ff h 100008 h 1007b9 h tx scq control block not used
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 152 8.2.1 transmit service class queue (tx scq) control block base address: 100000 h (400000 h byte) index: 4 h number of entries: 496 (1984 words) type: read/write long address = 100000 h + 40 h vo + 4 h service_class + offset byte address = 400000 h +100 h vo + 10 h service_class + offset 8.2.1.1 tx_scq_config offset: 0 h (0 h byte) type: read/write format: refer to the following table. table 26. transmit service class queue (tx scq) control block summary byte offset long offset name read or write description 0 h 0 h tx_scq_config r/w the exponents of the maximum and congested queue depths for this sc. 4 h 1 h tx_scq_state r/w (init only) the current queue depth and congestion state for this sc. 8 h 2 h tx_scq_head/ tx_scq_out_fifo_head r/w (init only) for non-multicast queues, this is the head of the linked list. for multicast queues, this is the fifo read pointer. c h 3 h tx_scq_tail/ tx_scq_out_fifo_tail r/w (init only) for non-multicast queues, this is the tail of the linked list. for multicast queues, this is the fifo write pointer. field (bits) description not present (31:16) ram is not present in these bit locations. tx_scq_exp_max_qd (15:12) exponent of the maximum per-sc queue depth. initialize to the proper setting. limits the tx_scq_cur_qd to: tx_scq_cur_qd 1+2 tx_scq_exp_max_qd a value of 0 h causes all cells for this scq to be dropped. a value of f h limits this sc to 31744 cells. tx_scq_exp_cong_qd (11:8) exponent of the congested per-scq queue depth. initialize to the proper setting. the congestion state is entered when the threshold is exceeded, and the congestion state is exited when the queue length drops below 50 percent of this threshold. enables conges- tion management when: tx_scq_cur_qd > 1 + 2 tx_scq_exp_cong_qd a value of 0 h causes this scq to be in congestion at all times. a value of 1 h may not be used. a value of f h causes this scq to enter congestion at a depth of 31744 cells.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 153 8.2.1.2 tx_scq_state (internal structure) offset: 1 h (4 h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following table. 8.2.1.3 tx_scq_head/tx_scq_out_fifo_head (internal structure) offset: 2 h (8 h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following tables. not used (7:3) write with a 0 to maintain software compatibility with future versions. tx_scq_exp_weight (2:1) defines the weight of the this scq in the queue service decision algorithm. the weight is equal to: 2 (tx_scqexp_weight 2) this allows weights of 1, 4, 16, and 64. not used (0) write with a 0 to maintain software compatibility with future versions. field (bits) description not present (31:16) ram is not present in these bit locations. tx_scq_state (15) current scq congestion state. initialize to 0 h . tx_scq_cur_qd (14:0) current scq service class unicast queue depth. initialize to 0000 h . this count does not include cells that are stored in the per-channel resequencing pointer buffers. for unicast scs field (bits) description not present (31:16) ram is not present in these bit locations. tx_scq_head (15:0) the head of the queue for this scq. (continued) field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 154 8.2.1.4 tx_scq_tail/tx_scq_out_fifo_tail (internal structure) offset: 3 h (c h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following tables. for multicast scs field (bits) description not present (31:16) ram is not present in these bit locations. not used (15:5) write with a 0 to maintain software compatibility with future versions. tx_scq_out_fifo_head (4:0) the head of the output multicast fifo (that is, the read pointer). for unicast scs field (bits) description not present (31:16) ram is not present in these bit locations. tx_scq_tail (15:0) the tail of the queue for this sc. for multicast scs field (bits) description not present (31:16) ram is not present in these bit locations. not used (15:5) write with a 0 to maintain software compatibility with future versions. tx_scq_out_fifo_tail (4:0) the tail of the output multicast fifo (that is, the write pointer).
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 155 8.3 receive service class ram (rsc_ram) summary the rsc_ram contains the receive service class (rx sc) control block. figure 68 shows a memory map of the rsc_ram. figure 68. receive service class ram (rsc_ram) memory map d0 d15 110000 h 11013f h 110140 h 11017f h rx sc control block not used
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 156 8.3.1 receive service class (rx sc) control block base address: 110000 h (440000 h byte) index: 1 h number of entries: 64 (320 words) type: read/write address =110000 h + offset + service_class 8.3.1.1 rx_sc_config offset: 0 h (0 h byte) type: read/write format: refer to the following table. table 27. receive service class (rx sc) control block summary byte offset long offset name read or write description 0-fc h 0-3f h rx_sc_config r/w the exponents of the maximum and congested queue depths for this sc. 100-1fc h 40-7f h rx_sc_state r/w (init only) the current queue depth for this sc. 200-2fc h 80-bf h rx_sc_cur_chan r/w (init only) the current channel being serviced for this sc. 300-3fc h c0-ff h rx_sc_prev_chan r/w (init only) the previous channel serviced for this sc. 400-4fc h 100-13f h rx_sc_ch_count r/w (init only) the number of channels with cells currently queued. field (bits) description not present (31:16) ram is not present in these bit locations. rx_sc_exp_max_qd (15:12) exponent of the maximum per-scq depth. initialize to the proper setting. limits the rx_sc_cur_qd to: rx_sc_cur_qd 1+2 rx_sc_exp_max_qd a value of 0 h causes all cells for this sc to be dropped. a value of f h limits this sc to 31744 cells. rx_sc_exp_cong_qd (11:8) exponent of the congested per-scq depth. initialize to the proper setting. the conges- tion state is entered when the threshold is exceeded, and the congestion state is exited when the queue length drops below 50 percent of this threshold. enables congestion management when: rx_sc_cur_qd > 1 + 2 rx_sc_exp_cong_qd a value of 0 h causes this sc to be in congestion at all times. a value of 1 h may not be used. a value of f h causes this sc to enter congestion at a depth of 31744 cells. not used (7:3) write with a 0 to maintain software compatibility with future versions. rx_sc_exp_weight (2:1) defines the weight of the sc in the queue service decision algorithm. weight = 2 (rx_sc_exp_weight 2) this allows weights of 1, 4, 16, or 64. not used (0) write with a 0 to maintain software compatibility with future versions.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 157 8.3.1.2 rx_sc_state (internal structure) offset: 40 h (100 h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following table. 8.3.1.3 rx_sc_cur_chan (internal structure) offset: 80 h (200 h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following table. 8.3.1.4 rx_sc_prev_chan (internal structure) offset: c0 h (300 h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following table. field (bits) description not present (31:16) ram is not present in these bit locations. rx_sc_state (15) current per-congestion state. initialize to 0 h . rx_sc_cur_qd (14:0) current per-scq depth. initialize to 0. this count includes both unicast and multicast cells, as well as those cells in the resequence buffers. field (bits) description not present (31:16) ram is not present in these bit locations. not used (15:14) write with a 0 to maintain software compatibility with future versions. rx_sc_cur_chan (13:0) points to the channel that is currently being serviced or that was just serviced by the round-robin service. initialize to 0000 h . field (bits) description not present (31:16) ram is not present in these bit locations. not used (15:14) write with a 0 to maintain software compatibility with future versions. rx_sc_prev_chan (13:0) points to the channel that was just served before the current channel in the round-robin service. initialize to 0000 h .
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 158 8.3.1.5 rx_sc_ch_count (internal structure) offset:100 h (400 h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following table. field (bits) description not present (31:16) ram is not present in these bit locations. not used (15:14) write with a 0 to maintain software compatibility with future versions. rx_sc_ch_count (13:0) the number of channels with cells currently queued. initialize to 0000 h . ? increment when a new channel is added (that is, when a cell received from the receive utopia interface is the first cell of the channel). ? decrement when the last cell of a channel has been successfully transmitted to the switch fabric.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 159 8.4 virtual output control ram (vo_ram) summary the virtual output control ram (vo_ram) contains the following regions: ? transmit vo control block ? transmit sc control block ? transmit multicast sc control block figure 69 shows the vo_ram memory map. figure 69. virtual output control ram (vo_ram) memory map transmit multicast sc control block transmit sc control block transmit vo control block 12009f h 1200a0 h 1200bf h 1200c0 h 1200ff h 120000 h
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 160 8.4.1 transmit vo control block address base: 120000 h (480000 h byte) index: 1 h number of entries: a0 h type: read/write 8.4.1.1 tx_vo_config offset: 0 h (0 h byte) type: read/write index: 1 h number of entries: 31 format: refer to the following table. table 28. transmit vo control block summary byte offset long offset name read or write description 0-78 h 0-1e h tx_vo_config r/w vo configuration. 7c h 1f h not used r/w write with a 0 to maintain software compatibility with future versions. 80-f8 h 20-3e h tx_vo_state r/w vo state. fc h 3f h not used r/w write with a 0 to maintain software compatibility with future versions. 100-178 h 40-5e h tx_vo_cells_pres r/w bit field of the scs with cells present for each vo. 17c h 5f h not used r/w write with a 0 to maintain software compatibility with future versions. 180-1f8 h 60-7e h tx_vo_service_state_0 r/w state word 0 of the service algorithm for this vo. 1fc h 7f h not used r/w write with a 0 to maintain software compatibility with future versions. 200-278 h 80-9e h tx_vo_service_state_1 r/w state word 1 of the service algorithm for this vo. 27c h 9f h not used r/w write with a 0 to maintain software compatibility with future versions. field (bits) description not present (31:16) ram is not present in these bit locations. tx_vo_exp_max_qd (15:12) exponent of the maximum per-vo queue depth. initialize to the proper setting. limits the tx_vo_cur_qd to: tx_vo_cur_qd 1+2 tx_vo_exp_max_qd a value of 0 h causes all cells for this vo to be dropped. a value of f h limits this sc to 31744 cells.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 161 8.4.1.2 tx_vo_state (internal structure) offset: 20 h (80 h byte) type: read/write C do not write after sw_reset (refer to sw_reset on page 101 ) is deasserted. index: 1 h number of entries: 31 format: refer to the following table. 8.4.1.3 tx_vo_cells_pres (internal structure) offset: 40 h (100 h byte) read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. index: 1 h number of entries: 31 format: refer to the following table. tx_vo_exp_cong_qd (11:8) exponent of the congested vo queue depth. initialize to the proper setting. the conges- tion state is entered when the threshold is exceeded, and the congestion state is exited when the queue length drops below 50 percent of this threshold. enables congestion management when: tx_vo_cur_qd > 1 + 2 tx_vo_exp_cong_qd a value of 0 h causes this vo to be in congestion at all times. a value of 1 h may not be used. a value of f h causes this vo to enter congestion at a depth of 31744 cells. not used (7:0) write with a 0 to maintain software compatibility with future versions. field (bits) description tx_vo_cong_st (15) congestion state bit for the same sc congestion determination. initialize to 0. this bit is read-only while cells are flowing. tx_vo_cur_qd (14:0) current vo queue depth. this is the count of the unicast cells queued for this vo. ini- tialize to 0000 h . this field is maintained by a state machine and is read-only after initial- ization. field (bits) description not present (31:16) ram is not present in these bit locations. tx_vo_cells_pres(15) (15) cells are present in the transmit scq 15 for vo = index. initialize to 0. tx_vo_cells_pres(14) (14) cells are present in transmit scq 14 for vo = index. initialize to 0. (continued) field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 162 8.4.1.4 tx_vo_service_state_0 (internal structure) offset: 60 h (180 h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following table. 8.4.1.5 tx_vo_service_state_1 (internal structure) offset:80 h (200 h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following table. tx_vo_cells_pres(0) (0) cells are present in the tranmsit scq 0 for vo = index. initialize to 0. field (bits) description not present (31:16) ram is not present in these bit locations. tx_vo_gp_ptr (15:12) pointer to 1 of the 12 gp sc queues. initialize to 0000. tx_vo_gp_weight_cnt (11:6) current weight count for the gp sc being serviced. initialize to 000000. tx_vo_sc2_weight_cnt (5:0) current weight count for the strict priority 2 class being serviced. initialize to 000000. field (bits) description not present (31:16) ram is not present in these bit locations. tx_vo_sc1_weight_cnt (15:10) current weight count for the strict priority 1 class being serviced. initialize to 000000. tx_vo_sc2_ptr (9) points to one of the two strict priority 2 scqs. initialize to 0. tx_vo_sc1_ptr (8) points to one of the two strict priority 1 scqs. initialize to 0. not used (7) write with a 0 to maintain software compatibility with future versions. tx_vo_time_slot_ptr (6:0) points to one of the 128 timeslot scs in the tx_service_table (refer to tx_service_table on page 181 ). initialize to 0000000. (continued) field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 163 8.4.2 transmit sc control block base address: 1200a0 h (480280 h byte) index: 2 h number of entries: 16 (32 words) type: read/write long address = 1200a0 h + 2 h service_class + offset byte address = 480280 h + 8 h service_class + offset 8.4.2.1 tx_sc_config offset: 0 h (0 h byte) type: read/write format: refer to the following table. table 29. transmit sc control block summary byte offset long offset name read or write description 0 h 0 h tx_sc_config r/w sc configuration word. this word defines the config- uration of a set of scs that stretch across all the trans- mit vos. this field is not present in the receive direction. initialize to the proper value. this word may be modified during cell flow. 4 h 1 h tx_sc_state r/w sc state. this word controls the congestion state of the set of same scs. initialize to 0. field (bits) description not present (31:16) ram is not present in these bit locations. tx_exp_max_sc_qd (15:12) exponent of the maximum per-sc queue depth. initialize to the proper setting. limits the tx_sc_cur_qd to: tx_sc_cur_qd 1+2 tx_sc_exp_max_qd a value of 0 h causes all cells for this sc to be dropped. a value of f h limits this sc to 31744 cells. tx_exp_cong_sc_qd (11:8) exponent of the congested per-sc queue depth. initialize to the proper setting. the con- gestion state is entered when the threshold is exceeded, and the congestion state is exited when the queue length drops below 50 percent of this threshold. enables conges- tion management when: tx_sc_cur_qd > 1 + 2 tx_sc_exp_cong_qd a value of 0 h causes this sc to be in congestion at all times. a value of 1 h may not be used. a value of f h causes this sc to enter congestion at a depth of 31744 cells. not used (7:0) write with a 0 to maintain software compatibility with future versions.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 164 8.4.2.2 tx_sc_state (internal structure) offset: 1 h (4 h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following table. 8.4.3 transmit multicast sc control block summary base address: 1200c0 h (480300 h byte) index: 4 h number of entries: 8 (64 words) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. long address = 200c0 h + 8 h ( service_class mod 8) + offset byte address = 480300 h +20 h ( service_class mod 8) + offset field (bits) description not present (31:16) ram is not present in these bit locations. tx_sc_cong_st (15) congestion state bit for the sc congestion determination. initialize to 0. this bit is read- only while cells are flowing. tx_sc_cur_qd (14:0) current scq depth. this is the count of the cells queued in all sc n across the vos. ini- tialize to 0000 h . this field is maintained by a state machine and is read-only after initial- ization. table 30. transmit multicast sc control block summary byte offset long offset name read or write description 0 h 0 h tx_sc_mc_in_fifo_head r/w head of the multicast input fifo for this sc. 4 h 1 h tx_sc_mc_in_fifo_tail r/w tail of the multicast input fifo for this sc. 8 h 2 h tx_sc_mc_bottle r/w bottlenecked vo for multicast in this sc. c h 3 h tx_sc_mc_next_header_ptr r/w the next multicast linked list entry (refer to sec- tion mc_list on page 195 ) to be transferred into an scq output fifo. 10-1c h 4-7 h reserved r/w initialize to 0 at initial setup. software modifi- cations to this location after setup may cause incorrect operation.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 165 8.4.3.1 tx_sc_mc_in_fifo_head (internal structure) offset: 0 h (0 h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following table. 8.4.3.2 tx_sc_mc_in_fifo_tail (internal structure) offset: 1 h (4 h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following table. 8.4.3.3 tx_sc_mc_bottle (internal structure) offset: 2 h (8 h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following table. field (bits) description not present (31:16) ram is not present in these bit locations. not used (15:12) write with a 0 to maintain software compatibility with future versions. tx_sc_mc_in_fifo_head (11:0) head of the multicast input fifo for this sc. initialize to 0. field (bits) description not present (31:16) ram is not present in these bit locations. not used (15:12) write with a 0 to maintain software compatibility with future versions. tx_sc_mc_in_fifo_tail (11:0) tail of the multicast in_fifo for this sc. initialize to 0. field (bits) description not present (31:16) ram is not present in these bit locations. not used (15:5) write with a 0 to maintain software compatibility with future versions. tx_sc_mc_bottle (4:0) bottlenecked scq for multicast in this sc. initialize to 0.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 166 8.4.3.4 tx_sc_mc_next_header_ptr (internal structure) offset: 3 h (c h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following table. field (bits) description not present (31:16) ram is not present in these bit locations. tx_sc_mc_next_header_ptr (15:0) the next header of the multicast linked list entry (refer to section mc_list on page 195 ) to be transferred out to an scq output fifo. initialize to 0.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 167 8.5 receive switch fabric control ram (rsf_control) summary note: all registers in this ram contain state information. no configuration or initialization is necessary. the only foreseen uses for this information are in system- and board-level diagnostics and/or debug. base address:130000 h (4c0000 h byte) index: 5 h number of entries: 8 (40 words) type: read/write long address = 130000 h + long_offset + rsf_buffer_number byte address = 4c0000 h + byte_offset + rsf_buffer_number 8.5.1 rx_rsf_config (internal structure) offset: 0 h (0 h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following table. table 31. receive switch fabric control ram (rsf_control) summary byte offset long offset name read or write description 0 h 0 h rx_rsf_config r/w the channel configuration of the cell in the receive switch fabric (rsf) transmission. 20 h 8 h rx_rsf_tag r/w the tag word for the cell intended for rsf transmission. note: this word also contains outchan(12:0). 40 h 10 h rx_rsf_new_vpi_vci r/w the new vpi and vci for the cell intended for rsf transmission. note: this word also contains outchan(15:13). 60 h 18 h rx_rsf_sn_chan r/w the sequence number and channel number for the cell intended for rsf transmission 80 h 20 h rx_rsf_er_cell_ptr r/w the explicit rate (er) and cell buffer pointer for the cell intended for rsf transmission. field (bits) description rx_rsf_config (31:0) the snapshot of the rx_ch_config of the channel where this cell originated. for information on rx_ch_config, refer to section rx_ch_tag on page 185 .
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 168 8.5.2 rx_rsf_tag (internal structure) offset: 8 h (20 h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following table. 8.5.3 rx_rsf_new_vpi_vci (internal structure) offset: 10 h (40 h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following table. 8.5.4 rx_rsf_sn_chan (internal structure) offset: 18 h (60 h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following table. field (bits) description rx_rsf_tag (31:0) the contents of the rx_ch_tag of the channel from which this cell originated. bits (7:4) contain out- chan(15:12). for information on rx_ch_tag, refer to section rx_ch_tag on page 185 . field (bits) description vpmode_ch (31) indicates the entry is valid vpc. vc_trans (30) indicates the vc is to be translated. initialize to the proper setting. not used (29:28) write with a 0 to maintain software compatibility with future versions. rsf_outchan_new_vpi (27:16) the outchan(11:0) or vpi value to be used. new_vci (15:0) the vci value to be used when translation is enabled by vc_trans. initialize to the proper setting. field (bits) description efci (31) explicit forward congestion indication bit to or into the outgoing data cells. not used (30:22) write with a 0 to maintain software compatibility with future versions. rx_rsf_sn (21:16) the sn for the cell pending, or that has completed, rsf transmission.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 169 8.5.5 rx_rsf_er_cell_ptr (internal structure) offset: 20 h (80 h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following table. 8.6 transmit switch fabric control ram (tsf_control_ram) summary note: all registers in this ram contain state information. no configuration or initialization is necessary. the only foreseen uses for this information are in system- and board-level diagnostics and/or debug. 8.6.1 tx_tsf_sn_chan (internal structure) base address: 140000 h (500000 h byte) index: 1 h number of entries: 12 type: read-only long address = 140000 h + tsf_buffer_number byte address = 500000 h + 4 tsf_buffer_number format: refer to the following table. rx_rsf_chan (13:0) the receive channel number from which this cell originated. field (bits) description rx_rsf_er (31:16) the er value to be sent in the payload of this cell pending rsf transmission if it is an rm cell. rx_rsf_cell_ptr (15:0) the cell pointer address of the cell pending, or that has completed, rsf transmission. field (bits) description not present (31:28) ram is not present in these bit locations. tx_tsf_clp_pti (27:24) the clp and pti for the cell received from the transmit switch fabric (tsf). not used (23:22) driven with a 0. mask on reads to maintain software compatibility with future versions. tx_tsf_sn (21:16) the sequence number of the cell received from the tsf. tx_tsf_outchan (15:0) the transmit outchan channel number of the cell received from the tsf. (continued) field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 170 8.7 test access to the receive utopia ram (ru_ram) base address: 150000 h (540000 h byte) index: 1 h number of entries: 64 (four cells) type: read/write during sw_reset (refer to sw_reset on page 101 ). format: refer to the following table receive utopia cell buffer summary (internal structure) base address: 1500000 h (5400000 h byte) index: 10 h entry number: 4 h type: read/write: during sw_reset (refer to sw_reset on page 101 ). long address = 1500000 h + entry_number 10 h field (bits) description rx_utopia_ram (31:0) test access to the ru_ram. table 32. receive utopia cell buffers summary offset cell 31:24 23:16 15:8 7:0 0 vpi(11:4) vpi(3:0), vci(15:12) vci(11:4) vci(3:0), pti, clp 1 payload 0 payload 1 payload 2 payload 3 2 payload 4 payload 5 payload 6 payload 7 3 payload 8 payload 9 payload 10 payload 11 4 payload 12 payload 13 payload 14 payload 15 5 payload 16 payload 17 payload 18 payload 19 6 payload 20 payload 21 payload 22 payload 23 7 payload 24 payload 25 payload 26 payload 27 8 payload 28 payload 29 payload 30 payload 31 9 payload 32 payload 33 payload 34 payload 35 10 payload 36 payload 37 payload 38 payload 39 11 payload 40 payload 41 payload 42 payload 43 12 payload 44 payload 45 payload 46 payload 47 13 00 h 000, vi not used not used 14 not used not used not used not used 15 not used not used not used not used
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 171 8.8 test access to the transmit utopia ram (tu_ram) address: 160000 h (580000 h byte) index: 1 h number of entries: 64(four cells) type: read/write during sw_reset (refer to sw_reset on page 101 ). format: refer to the following table. transmit utopia cell buffer summary (internal structure) base address: 160000 h (580000 h byte) index:4 h type: read/write during sw_reset (refer to sw_reset on page 101 ). long address = 160000 h + entry_number 10 h field (bits) description tx_utopia_ram (31:0) test access to the tu_ram. table 33. transmit utopia cell buffers summary offset cell 31:24 23:16 15:8 7:0 0 vpi(11:4) vpi(3:0), vci(15:12) vci(11:8) vci(3:0), pti, clp 1 payload 0 payload 1 payload 2 payload 3 2 payload 4 payload 5 payload 6 payload 7 3 payload 8 payload 9 payload 10 payload 11 4 payload 12 payload 13 payload 14 payload 15 5 payload 16 payload 17 payload 18 payload 19 6 payload 20 payload 21 payload 22 payload 23 7 payload 24 payload 25 payload 26 payload 27 8 payload 28 payload 29 payload 30 payload 31 9 payload 32 payload 33 payload 34 payload 35 10 payload 36 payload 37 payload 38 payload 39 11 payload 40 payload 41 payload 42 payload 43 12 payload 44 payload 45 payload 46 payload 47 13 not used not used not used not used 14 not used not used not used not used 15 not used not used not used not used
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 172 8.9 test access to receive switch element ram (rs_ram) address:170000 h (5c0000 h byte) index: 1 h number of entries: 128 (eight cells) type: read/write during sw_reset (refer to sw_reset on page 101 ) . format: refer to the following table. field (bits) description rx_switch_element_ram (31:0) test access to the rs_ram.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 173 8.10 test access to transmit swith element ram (ts_ram) address: 180000 h (600000 h byte) index: 1 h number of entries: 192 (12 cells) type: read/write during sw_reset (refer to sw_reset on page 101 ). format: refer to the following table. 9 external ram memory map 9.1 external ram summary the external ram contains: ? address lookup ram (al_ram) ? channel ram (ch_ram) ? channel head/tail and statistics ram (ab_ram) ? receive cell buffer sdram/sgram (rx_dram) ? transmit cell buffers sdram/sgram (tx_dram) the following is a memory map of the external ram, including addresses for the possible sram_config values. notes: ? all ports marked as reserved must be initialized to 0 at initial setup. software modifications to these locations after setup may cause incorrect operation. ? all read/write port bits marked not used must be written with the value 0 to maintain software com- patibility with future versions. ? all read-only port bits marked not used are driven with a 0 and should be masked off by the software to maintain compatibility with future versions. field (bits) description tx_switch_element_ram (31:0) test access to the ts_ram. byte address long address name description 800000 h 200000 h address lookup ram (al_ram) contains the address lookup tables, linked lists, and multicast pointer fifos. 1000000 h 400000 h channel ram (ch_ram) contains the channel tables. 1800000 h 600000 h ab_ram contains the head and tail pointers for the receive channel queues. 2000000 h 800000 h receive cell buffer sdram/sgram (rx_dram_register) receive buffer sdram/sgram. 3000000 h c00000 h transmit cell buffers sdram/sgram (tx_dram_register) transmit buffer sdram/sgram.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 174 9.2 address lookup ram (al_ram) table 34 summarizes the contents of the al_ram. table 34. address lookup ram (al_ram) summary byte offset long offset name read or write description 800000 h 200000 h vi_vpi_table r/w the first lookup is to this table. for vpcs, this lookup deter- mines the channel number directly. for vccs, this deter- mines the number of vci bits to use and the start of a block in the channel number table. if al_ram_config = 0: 808000 h if al_ram_config = 1: 810000 h if al_ram_config = 2: 820000 h if al_ram_config = 3: 880000 h if al_ram_config = 0: 202000 h if al_ram_config = 1: 204000 h if al_ram_config = 2: 208000 h if al_ram_config = 3: 220000 h vci_table r/w lookup table to determine the receive channel number (rx_chan_num) for vccs. refer to multicast cell instance control block (internal structure) on page 177 . refer to multicast cell instance control block (internal structure) on page 177 . multicast cell instance control block (internal structure) r/w header and cell pointer for multicast input and output fifo entries. if al_ram_config = 0: 838000 h if al_ram_config = 1: 870000 h if al_ram_config = 2: 8c0000 h if al_ram_config = 3: 9c0000 h if al_ram_config = 0: 20e000 h if al_ram_config = 1: 21c000 h if al_ram_config = 2: 230000 h if al_ram_config = 3: 270000 h rx_next_cell (internal structure) r/w index to the next cell in the receive per-channel linked list. if al_ram_config = 0: 830000 h if al_ram_config = 1: 860000 h if al_ram_config = 2: 8a0000 h if al_ram_config = 3: 980000 h if al_ram_config = 0: 20c000 h if al_ram_config = 1: 218000 h if al_ram_config = 2: 228000 h if al_ram_config = 3: 260000 h transmit cell buffer control block (internal structure) r/w for unicast cells, this is the index to the next cell in the transmit per-scq linked list. for multicast cells, this is the background processor control block. if al_ram_config = 0: 80c000 h if al_ram_config = 1: 820000 h if al_ram_config = 2: 840000 h if al_ram_config = 3: 900000 h if al_ram_config = 0: 203000 h if al_ram_config = 1: 208000 h if al_ram_config = 2: 210000 h if al_ram_config = 3: 240000 h service order con- trol block (internal structure) r/w timeslot-based priority table for receive and transmit scs.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 175 9.2.1 vi_vpi_table the first lookup is to this table. for vpcs, this lookup determines the channel number directly. for vccs, this determines the number of vci bits to use and the start of a block in the channel number table. base address: 200000 h (800000 h byte) index: 1 h number of entries: up to 128k long address: 200000 h + shift_left ((vi mod vi_conf), num_vpi) + vp mod num_vpi for num_vi, refer to num_vi on page 104 . vi_conf = 1 for num_vi=0 vi_conf = 4 for num_vi=1 vi_conf = 32 for num_vi=2 for num_vpi values, refer to table 35: type: read/write format: refer to the following tables. table 35. determining the num_vpi value if al_ram_config = if num_vi = 012 0 num_vpi = 12 num_vpi = 11 num_vpi = 8 1 num_vpi = 12 num_vpi = 12 num_vpi = 9 2 num_vpi = 12 num_vpi = 12 num_vpi = 10 3 num_vpi = 12 num_vpi = 12 num_vpi = 12 table 36. vi_vpi_table entry if vpc_entry = 1 field (bits) description not present (31:16) ram is not present in these bit locations. vpc_entry (15) indicates the entry is a valid vpc. initialize to the proper setting. not used (14) write with a 0 to maintain software compatibility with future versions. rx_chan_num (13:0) the receive channel number. table 37. vi_vpi_table entry if vpc_entry = 0 field (bits) description not present (31:16) ram is not present in these bit locations. vpc_entry (15) indicates the entry is a valid vpc. initialize to the proper setting.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 176 9.2.2 vci_table the vci_table determines the channel number for vccs. base address (refer to al_ram_config on page 105 ): if al_ram_config = 0, then the base address is 202000 h (808000 h byte). if al_ram_config = 1, then the base address is 204000 h (810000 h byte). if al_ram_config = 2, then the base address is 208000 h (820000 h byte). if al_ram_config = 3, then the base address is 220000 h (880000 h byte). index: 1 h number of entries: if al_ram_config = 0, then the entry number is 4k. if al_ram_config = 1, then the entry number is 16k. if al_ram_config = 2, then the entry number is 32k. if al_ram_config = 3, then the entry number is 64k. type: read/write address = base_address + entry_number format: refer to the following table. vcc_entry (14) indicates that at least one valid vcc is referenced in the table pointed to by this entry. initial- ize to the proper setting. vci_bits (13:10) the number of vci bits to use minus 1. the valid entries are 15 down to 4. block_offset (9:0) the offset ? 32 within the channel number block for this vi/vp within the channel number table. for al_ram_config = 3 (refer to al_ram_config on page 105 ), a block_offset(10) bit is needed. if vci_bits = f h , then block_offset(10) = 0. oth- erwise, block_offset(10) = incoming cell vpi (0). field (bits) description not present (31:16) ram is not present in these bit locations. not used (15:14) write with a 0 to maintain software compatibility with future versions. rx_chan_num (13:0) the receive channel number. table 37. vi_vpi_table entry if vpc_entry = 0 (continued) field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 177 9.2.3 multicast cell instance control block (internal structure) base address: x h for input fifos (refer to al_ram_config on page 105 ): if al_ram_config = 0 h , the base address is 206000 h (818000 h byte). if al_ram_config = 1 h , the base address is 210000 h (840000 h byte). if al_ram_config = 2 h , the base address is 220000 h (880000 h byte). if al_ram_config = 3 h , the base address is 250000 h (940000 h byte). for output fifos: if al_ram_config = 0 h , the base address is 208000 h (820000 h byte). if al_ram_config = 1 h , the base address is 214000 h (850000 h byte). if al_ram_config = 2 h , the base address is 214000 h (850000 h byte). if al_ram_config = 3 h , the base address is 258000 h (960000 h byte). index: 2 h entry number: for input fifos (refer to al_ram_config on page 105 ): if al_ram_config = 0 h , the entry number is 512. if al_ram_config = 1 h , the entry number is 1k. if al_ram_config = 2 h , the entry number is 1k. if al_ram_config = 3 h , the entry number is 2k. for output fifos: if al_ram_config = 0 h , the entry number is 32. if al_ram_config = 1 h , the entry number is 32. if al_ram_config = 2 h , the entry number is 32. if al_ram_config = 3 h , the entry number is 32. type: read/write byte offset long offset name read or write description 0 h 0 h mc_header_ptr r/w (init only) for the input fifo, this is the outchan from the cell. for the output fifo, this is the pointer to the entry in the mc header translation table for this entry. 4 h 1 h mc_cell_ptr r/w (init only) pointer to the cell buffer containing the multicast cell to be replicated.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 178 9.2.3.1 mc_header_ptr (internal structure) offset: 0 h (0 h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following table. 9.2.3.2 mc_cell_ptr (internal structure) offset: 1 h (4 h byte) type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following table. field (bits) description not present (31:16) ram is not present in these bit locations. mc_header_ptr (15:0) for the input fifo, this is the outchan from the cell. for the output fifo, this is the pointer to the entry in the mc header translation table for this entry. field (bits) description not present (31:16) ram is not present in these bit locations. mc_cell_ptr (15:0) the pointer to the cell buffer containing the multicast cell to be replicated.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 179 9.2.4 rx_next_cell (internal structure) base address (refer to al_ram_config on page 105 ): if al_ram_config = 0 h , the base address is 20e000 h (838000 h byte). if al_ram_config = 1 h , the base address is 21c000 h (870000 h byte). if al_ram_config = 2 h , the base address is 230000 h (8c0000 h byte). if al_ram_config = 3 h , the base address is 270000 h (9c0000 h byte). entry number: if al_ram_config = 0 h , the entry number is 8k. if al_ram_config = 1 h , the entry number is 16k. if al_ram_config = 2 h , the entry number is 64k. if al_ram_config = 3 h , the entry number is 64k. type: read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. format: refer to the following table. field (bits) description not present (31:16) ram is not present in these bit locations. rx_next_cell (15:0) index to the next cell in the receive per-channel linked list. initialize in an incrementing pattern starting with 1 h in the first location.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 180 9.2.5 transmit cell buffer control block (internal structure) base address (refer to al_ram_config on page 105 ): if al_ram_config = 0 h , the base address is 20c000 h (830000 h byte). if al_ram_config = 1 h , the base address is 218000 h (860000 h byte). if al_ram_config = 2 h , the base address is 228000 h (8a0000 h byte). if al_ram_config = 3 h , the base address is 260000 h (980000 h byte). index: 1 h entry number: if al_ram_config = 0 h , the entry number is 8k. if al_ram_config = 1 h , the entry number is 16k. if al_ram_config = 2 h , the entry number is 32k. if al_ram_config = 3 h , the entry number is 64k. read/write C do not write while sw_reset (refer to sw_reset on page 101 ) is deasserted. if the arriving cell is unicast field (bits) description not present (31:16) ram is not present in these bit locations. tx_next_cell (15:0) index to the next cell in the transmit per-scq linked list. initialize in an incrementing pattern starting with 1 h in the first location. if arriving cell is multicast field (bits) description not present (31:16) ram is not present in these bit locations. tx_mc_enq_pend (15) 1 the background processor is still queuing cells. 0 the background processor has finished queuing this cell. not used (14) write with a 0 to maintain future software compatibility. tx_mc_count (13:0) count of times this cell has been enqueued.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 181 9.2.6 service order control block (internal structure) if al_ram_config = 0 h , then the base address is 203000 h (80c000 h byte). if al_ram_config = 1 h , then the base address is 208000 h (820000 h byte). if al_ram_config = 2 h , then the base address is 210000 h (840000 h byte). if al_ram_config = 3 h , then the base address is 240000 h (900000 h byte). index: 1 h number of entries: 32 type: read/write 9.2.6.1 tx_service_table the tx_service_table is configured to provide an scq with a minimum cell rate. when no strict cell is present, the queue service algorithm examines the sc named and serves a cell from that class if there is one, advancing the pointer to this table. one of these tables exists for each vo. each table is 127 entries long (the 128 th entry is not used). type: read/write long base offset: base_address + 128 vo + entry index: 1 h number of entries: 128 format: refer to the following table. table 38. service order control block summary index name read or write description 0-1e h tx_service_table r/w table of the sc to serve if there are no cells in any of the strict scs for the transmit direction for vo = index. 1f h rx_service_table r/w table of the sc to serve if there are no cells in any of the strict scs for the receive direction. field (bits) description not present (31:16) ram is not present in these bit locations. not used (15:4) write with a 0 to maintain software compatibility with future versions. first_sc (3:0) sc to service if there are no strict service cells. to create a null entry, enter one of the strict scs.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 182 9.2.6.2 rx_service_table the rx_service_table is configured to provide an scq with a minimum cell rate. when no strict cell is present, the queue service algorithm examines the sc named and serves a cell from that class if there is one, advancing the pointer to this table. type: read/write if rx_long_svc_tbl=0 long base offset: base_address + f80 h number of entries: 127 if rx_long_svc_tbl=1 (not valid if alram_config=0) long base offset: base_address + 1000 h if rx_4_rr_ptrs = 0 number of entries: 511 if rx_4_rr_ptrs = 1 number of entries: 4x511 index: 1 h format: refer to the following table. field (bits) description not present (31:16) ram is not present in these bit locations. not used (15:6) write with a 0 to maintain software compatibility with future versions. first_sc (5:0) sc to service if there are no strict service cells. to create a null entry, enter one of the strict scs.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 183 9.3 channel ram (ch_ram) table 39 summarizes the contents of the ch_ram. 9.3.1 channel control block base address: 400000 h (01000000 h byte) index:10 h entry number (refer to ch_ram_config on page 105 ) for ch_ram_config = 0 h , the entry number is from 0 to 2047. for ch_ram_config = 1 h , the entry number is from 0 to 4095. for ch_ram_config = 2 h , the entry number is from 0 to 8191. for ch_ram_config = 3 h , the entry number is from 0 to 16385. type: read/write long address: in the receive direction, the long address = 400000 h + rx_chan_num 10 h + long_offset in the transmit direction, the long address = 400000 h + outchan 10 h + long_offset . table 39. channel ram (ch_ram) summary byte offset long offset name read or write description 01000000 h 400000 h channel control block (ccb) r/w receive and transmit per-channel control block. 01000000 h 400000 h multicast control block r/w control block for transmit multicast linked lists. table 40. channel control block summary byte offset long offset name read or write description 0 h 0 h rx_ch_config r/w overall controls for channel. 4 h 1 h rx_ch_tag r/w switch fabric tag. 8 h 2 h rx_ch_new_vpi_vci r/w vpi/vci to which you want to translate. c h 3 h rx_ch_state r/w (init only) current channel state. 10 h 4 h not used r/w write with a 0 to maintain software compatibility with future versions. 14 h 5 h rx_ch_next_ch r/w (init only) the next channel in the round-robin linked list. 18 h 6 h reserved r/w (init only) initialize to 0 at initial setup. software modifications to this location after setup may cause incorrect operation. 1c h 7 h reserved r/w (init only) initialize to 0 at initial setup. software modifications to this location after setup may cause incorrect operation. 20 h 8 h rx_ch_seq_st r/w (init only) state of the sequencing algorithm. 24 h 9 h not used r/w write with a 0 to maintain software compatibility with future versions. 28 h a h tx_ch_config r/w overall controls for the channel.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 184 9.3.1.1 rx_ch_config offset: 0 h (0 h byte) type: read/write format: refer to the following table. 2c h b h tx_new_vpi_reseq_ptr r/w vpi to which you want to translate and the pointer to the resequencing buffer. 30 h c h tx_ch_state r/w (init only) current channel state. 34 h d h tx_ch_reseq_st r/w (init only) state of the resequencing algorithm. 38 h e h tx_ch_cells_sent r/w (init only) count of transmit cells sent. 3c h f h tx_ch_cells_drpd r/w (init only) count of transmit cells dropped. field (bits) description rx_ch_exp_max_qd (31:28) exponent of the maximum per-sc queue depth. initialize to the proper setting. limits rx_ch_cur_qd (refer to rx_ch_cur_qd on page 187 ) to: rx_ch_cur_qd 1+2 rx_ch_exp_max_qd a value of 0 h causes all cells for this channel to be dropped. a value of f h limits this channel to 31744 cells. rx_ch_exp_cong_qd (27:24) exponent of the congested channel queue depth. initialize to the proper setting. the congestion state is entered when the threshold is exceeded, and the congestion state is exited when the queue length drops below 50 percent of this threshold. enables conges- tion management when: rx_ch_cur_qd > 1 + 2 rx_ch_exp_cong_qd a value of 0 h causes this channel to be in congestion at all times. a value of 1 h may not be used. a value of f h causes this channel to enter congestion at a depth of 31744 cells. rx_ch_entry_present (23) initialize to 0, set other variables, then initialize to the proper setting. 1 indicates the entry is present and valid. 0 indicates the entry is disabled. drop any cells received at this index. not used (22) initialize to 0 to maintain future compatibility rx_ch_service_class (21:16) indicates the sc. rx_ch_en_clp_drop (15) initialize to the proper setting. 1 enables clp dropping when either the channel, the sc, or the device is in the congested state. 0 disables clp dropping above the congestion threshold. not used (14) write with a 0 to maintain software compatibility with future versions. table 40. channel control block summary (continued) byte offset long offset name read or write description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 185 9.3.1.2 rx_ch_tag offset: 1 h (4 h byte) type: read/write format: refer to the following table. rx_ch_en_aal5_epd (13) initialize to the proper setting. 1 enables aal5 early packet discard (epd) and packet tail discard (ptd) when either the channel, the sc, or the device is in the congested state. if the maximum threshold is reached, then the tail of the packet is discarded. if clp causes a cell to be dropped, then the tail is discarded. 0 disables aal5 epd and ptd. rx_ch_en_efci (12) enable efci insertion. 0 disables efci insertion. 1 enable efci insertion. reserved (11:8) initialize to 0 at initial setup. software modifications to these locations after setup may cause incorrect operation. rx_ch_seq_type (7:6) initialize to the proper setting. 11 reserved. 10 reserved. 01 supports sequencing of up to two cells allowing a 155 mbps vc. 00 no sequencing; allows a 78 mbps vc. the routing table at the other end of the connection must support the same resequencing mode for unicast connections. for multicast connections, this field may be set to either 00 or 01. rx_ch_sf_multicast (5) insert in the multicast (mc) cell bit in nibble 0 (refer to table on page 91 ). if 1, this channel is treated as multicast by the switch fabric. this must be the same as rx_ch_service_class(5) (refer to tx_ch_service_class on page 189 ). rx_ch_sf_spare (4) insert into the spare (sp) bit in nibble 0 (refer to table on page 91 ). rx_ch_switch_group (3:0) switch group to be used in nibble 1 as the cell is sent to the switch fabric. 3 h for rx_ch_service_class from 00 h to 07 h or 20 h to 27 h 2 h for rx_ch_service_class from 08 h to 0f h or 28 h to 2f h . 1 h for rx_ch_service_class from 10 h to 1f h or 30 h to 3f h . 0 h reserved. the above settings are highly recommended for unicast service classes (00 to 1f) to insure that high priority cells from the rx get high priority through the switch fabric (qse), and similarly for medium and low priority cells. the above settings are required for the multicast service classes (20 - 3f) to insure that the multicast backpressure mechanism works properly between the switch fabric and the qrt. the switch fabric gives high, medium or low bp, and the qrt must refrain from sending cells on the corresponding service classes. field (bits) description rx_ch_tag_0_6(3:0) (31:28) tag information inserted into se_d_out(3:0) immediately after the switch_group/queue field (refer to table starting on page 91 ). it is also inserted after tag_5(3:0). initialize to the proper setting. (continued) field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 186 notes: ? the qse interprets tag_2, tag_3, tag_0_6, and tag_1_7 as the mcg. 9.3.1.3 rx_ch_new_vpi_vci offset: 2 h (8 h byte) type: read/write format: refer to the following table. rx_ch_tag_1_7(3:0) (27:24) tag information inserted into se_d_out(3:0) immediately after tag_0(3:0). it is also inserted after the tag_0_6 is inserted the second time. initialize to the proper setting. rx_ch_tag_2(3:0) (23:20) tag information inserted into se_d_out(3:0) immediately after tag_1(3:0). initial- ize to the proper setting. rx_ch_tag_3(3:0) (19:16) tag information inserted into se_d_out(3:0) immediately after tag_2(3:0). initial- ize to the proper setting. rx_ch_tag_4(3:0) (15:12) tag information inserted into se_d_out(3:0) immediately after tag_3(3:0). initial- ize to the proper setting. rx_ch_tag_5(3:0) (11:8) tag information inserted into se_d_out(3:0) immediately after tag_4(3:0). initial- ize to the proper setting. rx_ch_tag_8(3:0) (7:4) tag information inserted into se_d_out(3:0) immediately after tag_7(3:0). initial- ize to the proper setting. when connected across the fabric to a qse, this field is out- chan(15:12). rx_ch_tag_9(3:0) sp(1:0),mb,p (3:0) tag information inserted into se_d_out(3:0) immediately after tag_8(3:0). set mb to 1 to enable the marked cell counters. set p to 1 to create even parity. set p to 0 to create odd parity to test the parity checker on the transmit side. initialize to the proper setting. field (bits) description not used (31) write with a 0 to maintain software compatibility with future versions. rx_ch_vci_trans (30) indicates that the vci is to be translated. initialize to the proper setting. not used (29:28) write with a 0 to maintain software compatibility with future versions. rx_ch_outchan_new_vpi (27:16) outchan(11:0). this field is always used. initialize to the proper setting. rx_ch_new_vci (15:0) the vci value to be used when translation is enabled by rx_ch_vci_trans. initialize to the proper setting. field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 187 9.3.1.4 rx_ch_state (internal structure) offset: 3 h (c h byte) type: read/write format: refer to the following table. 9.3.1.5 rx_ch_next_ch/rx_ch_seq_ptr1 (internal structure) offset: 5 h (14 h byte) type: read/write format: refer to the following table. field (bits) description rx_ch_aal5_state (31:30) current aal5 state. 00 b the last cell was not an end-of-frame and was not dropped. 01 b the last cell received was an end-of-frame. 10 b the last cell was dropped. 11 b undefined. initialize to 00 b . this field is maintained by a state machine and is read-only after initial- ization. rx_ch_cell_rcvd (29) a cell has been received for this channel. initialize to 0. this bit may not be cleared. not used (28:22) write with a 0 to maintain software compatibility with future versions. rx_ch_last_cleared_sn (21:16) last cleared sequence numbered. initialize to 0. rx_ch_congested (15) 1 this channel is currently congested. 0 this channel is currently not congested. initialize to 0. this field is maintained by a state machine and is read-only after initial- ization. rx_ch_cur_qd (14:0) current per-channel queue depth. initialize to 0000 h . this field is maintained by a state machine and is read-only after initialization. field (bits) description rx_ch_seq_cell_ptr1 (31:16) pointer to the second outstanding cell. initialize to 0. this field is maintained by a state machine and is read-only after initialization. not used (15:14) write with a 0 to maintain software compatibility with future versions. rx_ch_next_ch (13:0) next channel in the round-robin service. initialize to 0000 h .
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 188 9.3.1.6 rx_ch_seq_st (internal structure) address: 8 h (20 h byte) type: read/write format: refer to the following tables. if rx_ch_seq_type = 00 b (one cell allowed to be outstanding) field (bits) description rx_ch_run_limited (31) indicates that this channel has been removed from the ring of channels for this sc because it has reached its limit. not used (30:18) write with a 0 to maintain software compatibility with future versions. rx_ch_seq_state0 (17:16) state of the cell sequencing state machine for cell pointer 0. initialize to 0. this field is maintained by a state machine and is read-only after initial- ization. 00 b rx_ch_seq_cell_ptr0 is empty. 01 b rx_ch_seq_cell_ptr0 is currently pending transmission. 10 b rx_ch_seq_cell_ptr0 received an onack on last transmission. 11 b rx_ch_seq_cell_ptr0 received an ack on last transmission. rx_ch_seq_cell_ptr0 (15:0) pointer to the first outstanding cell. initialize to 0. this field is maintained by a state machine and is read-only after initialization. if rx_ch_seq_type = 01 b (two cells allowed to be outstanding) field (bits) description rx_ch_run_limited (31) indicates this channel has been removed from the ring of channels for this sc because it has reached its limit. rx_ch_ptr_next_to_clr (30) resequencing state bit. initialize to 0. not used (29:20) write with a 0 to maintain software compatibility with future versions. rx_ch_seq_state (19:16) state of the cell reassembly state machines. initialize to 0. this field is maintained by a state machine and is read-only after initial- ization. (19:18) state bits for rx_ch_seq_cell_ptr1. (17:16) state bits for rx_ch_seq_cell_ptr0. rx_ch_seq_cell_ptr0 (15:0) pointer to the outstanding cell. initialize to 0. this field is maintained by a state machine and is read-only after initialization.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 189 9.3.1.7 tx_ch_config address: a h (28 h byte) type: read/write format: refer to the following table. field (bits) description tx_ch_exp_max_qd (31:28) exponent of the maximum per-sc queue depth. initialize to the proper setting. limits the tx_ch_cur_qd to: tx_ch_cur_qd 1+2 tx_ch_exp_max_qd a value of 0 h causes all cells for this channel to be dropped. a value of f h limits this chan- nel to 31744 cells. tx_ch_exp_cong_qd (27:24) exponent of the congested per-sc queue depth. initialize to the proper setting. the con- gestion state is entered when the threshold is exceeded, and the congestion state is exited when the queue length drops below 50 percent of this threshold. enables congestion man- agement when: tx_ch_cur_qd > 1+2 tx_ch_exp_cong_qd a value of 0 h causes this ch to be in congestion at all times. a value of 1 h may not be used. a value of f h causes this ch to enter congestion at a depth of 31744 cells. tx_ch_entry_present (23) initialize to 0, set other variables, then initialize to the proper setting. 1 indicates this channel is present and valid. 0 indicates this channel is disabled. drop any cells received at this index, but still update tx_ch_cells_sent and tx_ch_cells_drpd (refer to sections tx_ch_cells_sent on page 193 and tx_ch_cells_drpd on page 193 ). not used (22:20) write with a 0 to maintain software compatibility with future versions. tx_ch_service_class (19:16) indicates the transmit sc. tx_ch_en_clp_drop (15) initialize to the proper setting. 1 enables clp dropping when the channel, the sc, the ssc, the vo, or the device is in the congested state. 0 disables clp dropping above the congestion threshold. not used (14) write with a 0 to maintain software compatibility with future versions. tx_ch_en_aal5_epd (13) initialize to the proper setting. 1 enables aal5 early packet discard (epd) when the channel, the scq, the sc, the vo, or the device is in the congested state. if the queue depth reaches the maximum threshold, or if clp = 1 and the queue depth reaches the con- gestion threshold, the tail of the frame is dropped. 0 disables aal5 epd. tx_ch_en_efci (12) written with a 0 to maintain compatibility with future software versions. 1 enable efci. 0 disable efci. reserved (11:8) initialize to 0 at initial setup. software modifications to these locations after setup may cause incorrect operation.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 190 9.3.1.8 tx_new_vpi_reseq_ptr address: b h (2c h byte) type: read/write format: refer to the following tables. if tx__ch_service_class(3) = 1 (multicast) tx_ch_reseq_type (7:6) initialize to the proper setting. 11 reserved. 10 reserved. 01 supports resequencing of up to two cells, allowing a 155 mbps vc. 00 no resequencing, allowing a 78 mbps vc. the routing table at the other end of the connection must support the same resequencing mode for unicast connections. this field must be set to 00 for multicast connections. not used (5) write with a 0 to maintain software compatibility with future versions. tx_ch_uc_vo (4:0) the transmit utopia level 2 address of the phy interface for unicast cells. for multi- cast connections, this is the vo to use for vo congestion management. vo congestion management indicates only the unicast cells bound for that vo. if tx_ch_service_class(3) = 0 (unicast) field (bits) description tx_ch_vpi_trans (31) indicates the vpi is to be translated. initialize to the proper setting. not used (30:28) write with a 0 to maintain software compatibility with future versions. tx_ch_new_vpi (27:16) the vpi value to be used. initialize to the proper setting. not used (15:0) write with a 0 to maintain software compatibility with future versions. field (bits) description tx_ch_mc_vo (31:27) the transmit utopia level 2 address of the phy interface for the first multicast cell in this linked list. initialize to the proper setting. not used (26:17) write with a 0 to maintain software compatibility with future versions. tx_ch_replicate_cell (16) 1 make another copy of this cell. 0 do not make another copy of this cell. tx_ch_next_mc_header_pt r (15:0) index to the next translation field. initialize to the proper setting. (continued) field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 191 9.3.1.9 tx_ch_state (internal structure) address: c h (30 h byte) type: read/write format: refer to the following table. field (bits) description tx_ch_aal5_state (31:30) if tx_ch_reseq_type = 00 b (refer to tx_ch_reseq_type on page 190 ), the current aal5 congestion state. 00 b the last cell received was not an end-of-frame and was not dropped. 01 b the last cell received was an end-of-frame. 10 b the last cell received was dropped. 11 b undefined. initialize to 00 b . this field is maintained by a state machine and is read-only after initial- ization. tx_ch_cell_received (29) a cell was received for this channel. initialize to 0. this bit may not be cleared. reserved (28) initialize to 0 at initial setup. software modifications to this location after setup may cause incorrect operation. tx_ch_in_dropping (27) history bit that contains the result of past congestion management action when in 2-cell resequencing. initialize to 0. reserved (26:22) initialize to 0 at initial setup. software modifications to this location after setup may cause incorrect operation. tx_ch_run_start_sn (21:16) sequence number where the next run will start. initialize to 01 h . tx_ch_congested (15) 1 this channel is currently congested. 0 this channel is currently not congested. initialize to 0. this field is maintained by a state machine and is read-only after initialization. tx_ch_cur_qd (14:0) current per-channel queue depth. initialize to 0000 h . this field is maintained by a state machine and is read-only after device initialization.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 192 9.3.1.10 tx_ch_reseq_st address: d h (34 h byte) type: read/write format: refer to the following table. field (bits) description not used (31:29) write with a 0 to maintain software compatibility with future versions. tx_ch_recovery_state (28) state of the resequencer error recovery state machine. initialize to 0 b . this field is maintained by a state machine and is read-only after initial- ization. 0 b the machine indicates normal operation. 1 b the machine has seen a sequence number error and is attempting to recover. not used (27:25) write with a 0 to maintain software compatibility with future versions. tx_ch_stat_store_state (24:23) initialize to 0 b . this field is maintained by a state machine and is read-only after initial- ization. when tx_count_sent_clp = 0 (refer to tx_count_sent_clp on page 106 ), then bit 23 means: 0 b if tx_ch_reseq_state = empty (bit 22 in this register is set to 0 b ), then the counts are accurate. otherwise, tx_ch_cells_sent (refer to tx_ch_cells_sent on page 193 ) is one too high. 1 b if tx_ch_reseq_state 1 empty, then the send count is one too high. otherwise, the tx_ch_cells_sent is one too high and tx_ch_cells_drpd (refer to tx_ch_cells_drpd on page 193 ) is one too low. when tx_count_sent_clp = 1, bit 23 is for the clp = 0 counter and bit 24 is for the clp = 1 counter. 0 b the machine has observed a cell count too many. 1 b the machine has observed correct accounting. tx_ch_reseq_state (22) state of the cell reassembly state machine. initialize to 0 b . this field is maintained by a state machine and is read-only after initialization. 0 b the tx_ch_reseq_cell_ptr is empty. 1 b the tx_ch_reseq_cell_ptr contains a received cell. tx_ch_dropped_store (21) 0 b indicates a cell was not dropped when the resequencer machine intended to store the cell. 1 b indicates a cell was dropped after the resequencer machine intended to store the cell. not used (20:17) write with a 0 to maintain software compatibility with future versions. tx_ch_reseq_oam_cell (16) 0 b indicates the cell pending resequencing is not an oam cell. 1 b indicates the cell pending resequencing is an oam cell. tx_ch_reseq_cell_ptr (15:0) the pointer to the outstanding cell. initialize to 0. this field is maintained by a state machine and is read-only after initialization.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 193 9.3.1.11 tx_ch_cells_sent address: e h (38 h byte) type: read/write (read-only after initialization) format: refer to the following table. 9.3.1.12 tx_ch_cells_drpd address: f h (3c h byte) type: read/write (read-only after initialization) format: refer to the following table. field (bits) description tx_ch_cells_sent (31:0) if tx_count_sent_clp = 0 (refer to tx_count_sent_clp on page 106 ), count of transmit cells sent. if tx_count_sent_clp = 1, count of transmit clp = 0 cells sent. count rolls over at ffffffff h . initialize to 00000000 h . read-only after initialization. field (bits) description tx_ch_cells_drpd (31:0) if tx_count_sent_clp = 0 (refer to tx_count_sent_clp on page 106 ), count of transmit cells dropped. if tx_count_sent_clp = 1, count of transmit clp = 1 cells sent. count rolls over at ffffffff h . initialize to 00000000 h . read-only after initialization.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 194 9.3.2 multicast control block base address:400000 h (1000000 h byte) index:10 h entry number (refer to ch_ram_config on page 105 ): for ch_ram_config = 0 h , the entry number is from 0 to 8191. for ch_ram_config = 1 h , the entry number is from 0 to 16385. for ch_ram_config = 2 h , the entry number is from 0 to 32767. for ch_ram_config = 3 h , the entry number is from 0 to 65534. note: the entry numbers listed above refer to a block of four words. table 41 describes how four entries fit into the space of one channel control block (ccb). each block of 16 words can be used for either one ccb or four multicast control blocks. type: read/write when multicasting in either direction, the long address = 400000 h + tx_ch_next_mc_header_ptr 4 h (refer to mc_header_ptr on page 177 ). table 41. multicast control block summary byte address long offset name read or write description 0 h 0 h mc_list r/w multicast linked list. 4 h 1 h mc_new_vpi_vci r/w multicast vpi/vci to which you want to translate. 8 h -c h 2-3 h not used r/w write with a 0 to maintain software compatibility with future versions. 10 h 4 h mc_list r/w multicast linked list. 14 h 5 h mc_new_vpi_vci r/w multicast vpi/vci to which you want to translate. 18 h -1c h 6-7 h not used r/w write with a 0 to maintain software compatibility with future versions. 20 h 8 h mc_list r/w multicast linked list. 24 h 9 h mc_new_vpi_vci r/w multicast vpi/vci to which you want to translate. 28 h -2c h a-b h not used r/w write with a 0 to maintain software compatibility with future versions. 30 h c h mc_list r/w multicast linked list. 34 h d h mc_new_vpi_vci r/w multicast vpi/vci to which you want to translate. 38 h -3c h e-f h not used r/w write with a 0 to maintain software compatibility with future versions.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 195 9.3.2.1 mc_list address: 0 h or 4 h or 8 h or c h (0 h or 10 h or 20 h or 30 h byte) type: read/write format: refer to the following table. 9.3.2.2 mc_new_vpi_vci offset: 1 h or 5 h or 9 h or d h (4 h or 14 h or 24 h or 34 h byte) type: read/write format: refer to the following table. field (bits) description tx_mc_vo (31:27) the transmit utopia vo for the next entry in the linked list. not used (26:17) write with a 0 to maintain software compatibility with future versions. tx_mc_replicate_cell (16) 1 make another copy of this cell. 0 do not make another copy of this cell. tx_mc_next_mc_header_ptr (15:0) index to the next translation field. initialize to the proper setting. field (bits) description tx_mc_vpi_trans (31) indicates the vpi is to be translated. initialize to the proper setting. tx_mc_vci_trans (30) indicates the vci is to be translated. initialize to the proper setting. not used (29:28) write with a 0 to maintain software compatibility with future versions. tx_mc_new_vpi (27:16) the vpi value to be used when translation is enabled by tx_mc_vpi_trans. initial- ize to the proper setting. tx_mc_new_vci (15:0) the vci value to be used when translation is enabled by tx_mc_vci_trans. initialize to the proper setting.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 196 9.4 abr_ram table 42 summarizes the contents of the ab_ram. 9.4.1 receive channel queue block base address: 600000 h (0180000 h byte) index: 2 h the long address = 600000 h + rx_chan_num 2 h + long_offset 9.4.1.1 rx_ch_head (internal structure) offset: 0 h (0 h byte) type: read/write format: refer to the following table. 9.4.1.2 rx_ch_tail (internal structure ) offset: 1 h (4 h byte) type: read/write format: refer to the following table. table 42. ab_ram summary byte offset long offset name read or write description 0180000 h 600000 h receive channel queue block r/w receive channel head and tail pointers. 0184000 h 610000 h receive channel sent/drop counters r/w receive channel sent/drop cell counters table 43. receive channel queue block summary address name read or write description 0 h rx_ch_head r/w head pointer of the receive channel queue. 1 h rx_ch_tail r/w tail pointer of the receive channel queue. field (bits) description not present (31:16) no ram is present in these bit positions. rx_queue_head (15:0) the head of the channel queue. field (bits) description not present (31:16) no ram is present in these bit positions. rx_queue_tail (15:0) the tail of the channel queue.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 197 9.4.2 receive channel statistics block base address: 610000 h (0184000 h byte) index: 4 h the long address = 610000 h + rx_chan_num 4 h + long_offset the receive channel statistics counters are only valid if the rx_stats bit in the rx_queue_engine_test register ( rx_queue_engine_test on page 123 ) is set to 1 9.4.2.1 rx_ch_sent (internal structure) offset: 0 h (0 h byte) type: read/write format: refer to the following table. 9.4.2.2 rx_ch_dropped (internal structure ) offset: 2 h (8 h byte) type: read/write format: refer to the following table. 9.5 sdram/sgram interface description the sdrams/sgrams are used in the qrt system to store the cells in the receive and transmit directions. before the sdrams/sgrams can be used, they must be prepared for operation. this section discusses setting up the sdram/sgram for normal operations, as well as test mode access by the microprocessor to check the data integrity of the sdram/sgram. table 44. receive channel queue block summary address name read or write description 0 h rx_ch_sent r/w cells sent from this chan- nel. 2 h rx_ch_dropped r/w cells dropped from this channel. field (bits) description rx_ch_sent (31:0) total cells sent from this channel. initialize to 0 field (bits) description rx_ch_dropped (31:0) total cells dropped from this channel. initialize to 0
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 198 the receive and transmit sdrams/sgrams are each mapped to a memory location of the microprocessor address space, and the addresses within the rams are accessed by an indirect addressing method. the rx_dram_register is mapped to address 2000000 and tx_dram_register is mapped to address 3000000. at this address space exists a 16-bit, read/write register. for all set-up operations and write operations, the microprocessor writes to this address port. for reading a sdram/sgram location, writes are initially performed to set up the read cycles, and then this sdram/sgram register is read to obtain the value at the desired sdram/sgram location. to perform a sdram/sgram operation, the corresponding access code (along with the address and data) is written to the microprocessor address port corresponding to the sdram/sgram. the sdram/sgram controller inside the qrt converts this access code to a sdram/ sgram access cycle obeying the signaling requirements of the sdram/sgram. access code instruction 0000 no op 0001 read b ank 0 0010 write b ank 0 0011 active bank 0 0100 reserved 0101 read b ank 1 0110 write b ank 1 0111 active bank 1 1000 reserved 1001 precharge 1010 autoref 1011 reserved 1100 l oad reg 1101 reserved 1110 self refresh
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 199 after powerup or after a sustained software reset, the transmit and receive sdrams/sgrams need to be initialized. the rx_dram_register runs in a burst-of-four mode, whereas the tx_dram_register runs in a burst-of-eight mode, so the mode register needs to be initial- ized differently. to initialize the sdram/sgram: chip 0 chip 1(sgram only) w-no op 00000000 h 00004000 h w-precharge both banks 93000000 h 93004000 h w-autorefresh a2000000 h a2004000 h w-autorefresh a2000000 h a2004000 h w-load register c2yy (yy = 32 for rx_dram_register, 33 for tx_dram_register) c2320000 h c2324000 h w-no op 00000000 h 00004000 h to write a location to the sdram/sgram (for example, location 0 h in bank 0 with 55555555 h ): w-active bank 0 32000000 h 32004000 h w-write bank 0 26000000 h 26004000 h to read the location of the sdram/sgram (for example, location 0 h in bank 0): w-active bank 0 32000000 h 32004000 h w-read bank 0 12000000 h 12004000 h r- value of the dram location to write a location to the sdram/sgram (for example, location 1234 h in bank 1with aaaaaaaa h ): w-active bank 1 72120000 h 72124000 h w-write bank 1 6a340000 h 6a344000 h 9.5.1 rx_dram_register address: 2000000 h (8000000 h byte) type: read/write field (bits) description rx_dram_access_code (31:28) the access code to control the type of sdram/sgram cycle. rx_dram_data (27:26) the data to be written to the dram. this 2-bit field is replicated 16 times and written to the 32-bit wide sdram/sgram. data of 00, 01, 10, and 11 correspond to dram data 00000000 h , 55555555 h , aaaaaaaa h , and ffffffff h . no other values of data can be written to the sdram/sgram. rx_dram_mi_select (25) 0 normal operation. 1 enables microprocessor access to the sdram/sgram.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 200 rx_dram_address (24:16) corresponds to the row address during active cycles and column address during read or write cycles. the msb is autoprecharge during channel associated signaling (cas) cycles (read or write). rx_dram_upper_addr (15:14) for sgram: buffer ram is organized as 2 chips with 512 rows each 00 b select sgram chip 0. 01 b select sgram chip 1. 10 b invalid. 11 b invalid. for sdram: buffer ram is organized as 2048 rows 00 b select rows 0 to 511 01 b select rows 512 to 1023. 10 b select rows 1024 to 1535 11 b select rows 1536 to 2047 reserved (13:0) initialize to 0 at initial setup. software modifications to this location after setup may cause incorrect operation. (continued) field (bits) description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 201 9.5.2 tx_dram_register address: 3000000 h (c000000 h byte) type: read/write field (bits) description tx_dram_access_code (31:28) the access code to control the type of sdram/sgram cycle. tx_dram_data (27:26) the data to be written to the sdram/sgram. this 2-bit field is replicated 16 times and written to the 32-bit wide sdram/sgram. data of 00, 01, 10, and 11 correspond to dram data 00000000 h , 55555555 h , aaaaaaaa h , and ffffffff h . no other val- ues of data can be written to the sdram/sgram. tx_dram_mi_select (25) select for microprocessor access to the sdram/sgram. write with a 0 for normal operation. tx_dram_address (24:16) corresponds to the row address during active cycles and column address during read or write cycles. the msb is autoprecharge during cas cycles (read or write). tx_dram_upper_addr (15:14) for sgram: buffer ram is organized as 2 chips with 512 rows each 00 b select sgram chip 0. 01 b select sgram chip 1. 10 b invalid. 11 b invalid. for sdram: buffer ram is organized as 2048 rows 00 b select rows 0 to 511 01 b select rows 512 to 1023. 10 b select rows 1024 to 1535 11 b select rows 1536 to 2047 reserved (13:0) initialize to 0 at initial setup. software modifications to this location after setup may cause incorrect operation.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 202 9.5.3 receive cell buffer sdram/sgram summary (internal structure) base address: 2000000 h (8000000 h byte) index: 10 h entry number (refer to al_ram_config on page 105 ): if al_ram_config = 0 h , the entry number is 8k. if al_ram_config = 1 h , the entry number is 16k. if al_ram_config = 2 h , the entry number is 64k. if al_ram_config = 3 h , the entry number is 64k. read/write: use rx_dram_register long address = 2000000 h + entry_number 10 h table 45. receive cell buffers sdram/sgram summary offset cell 31:24 23:16 15:8 7:0 0 vpi(11:4) vpi(3:0), vci(15:12) vci(11:4) vci(3:0) pti, clp 1 payload 0 payload 1 payload 2 payload 3 2 payload 4 payload 5 payload 6 payload 7 3 payload 8 payload 9 payload 10 payload 11 4 payload 12 payload 13 payload 14 payload 15 5 payload 16 payload 17 payload 18 payload 19 6 payload 20 payload 21 payload 22 payload 23 7 payload 24 payload 25 payload 26 payload 27 8 payload 28 payload 29 payload 30 payload 31 9 payload 32 payload 33 payload 34 payload 35 10 payload 36 payload 37 payload 38 payload 39 11 payload 40 payload 41 payload 42 payload 43 12 payload 44 payload 45 payload 46 payload 47 13 00 h 00 h 00 h 0 h , parity(3:0) 14 not used not used not used not used 15 not used not used not used not used
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 203 9.5.4 transmit cell buffer sdram/sgram summary (internal structure) base address: 3000000 h (c000000 h byte) index: 10 h entry number (refer to al_ram_config on page 105 ): if al_ram_config = 0 h , the entry number is 8k. if al_ram_config = 1 h , the entry number is 16k. if al_ram_config = 2 h , the entry number is 32k. if al_ram_config = 3 h , the entry number is 64k. read/write: use tx_dram_register long address = 3000000 h + entry_number 10 h table 46. transmit cell buffers sdram/sgram summary offset cell 31:24 23:16 15:8 7:0 0 parity(7:0) 00 h outchan(15:8) outchan(7:0) 1 vpi(11:4) vpi(3:0), vci(15:12) vci(11:4) vci(3:0), pti, clp 2 payload 0 payload 1 payload 2 payload 3 3 payload 4 payload 5 payload 6 payload 7 4 payload 8 payload 9 payload 10 payload 11 5 payload 12 payload 13 payload 14 payload 15 6 payload 16 payload 17 payload 18 payload 19 7 payload 20 payload 21 payload 22 payload 23 8 payload 24 payload 25 payload 26 payload 27 9 payload 28 payload 29 payload 30 payload 31 10 payload 32 payload 33 payload 34 payload 35 11 payload 36 payload 37 payload 38 payload 39 12 payload 40 payload 41 payload 42 payload 43 13 payload 44 payload 45 payload 46 payload 47 14 not used not used not used not used 15 not used not used not used not used
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 204 10 jtag jtag support the qrt supports the ieee boundary scan specification as described in the ieee 1149.1 standards. the test access port (tap) consists of the five standard pins, trstb, tck, tms, tdi and tdo, used to control the tap controller and the boundary scan registers. the trstb input is the active low reset signal used to reset the tap controller. tck is the test clock used to sample data on input, tdi and to output data on output, tdo. the tms input is used to direct the tap con- troller through its states. the basic boundary scan architecture is shown below. figure 70. boundary scan architecture the boundary scan architecture consists of a tap controller, an instruction regis- ter with instruction decode, a bypass register, a device identification register and a boundary scan register. the tap controller interprets the tms input and gener- ates control signals to load the instruction and data registers. the instruction reg- ister with instruction decode block is used to select the test to be executed and/or the register to be accessed. the bypass register offers a single bit delay from pri- boundary scan register control tdi tdo device identification register bypass register instruction register and decode trstb tms tck test access port controller mux dff select tri-state enable
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 205 mary input, tdi to primary output, tdo. the device identification register con- tains the device identification code. the boundary scan register allows testing of board inter-connectivity. the bound- ary scan register consists of a shift register place in series with device inputs and outputs. using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, tdo. in addition, patterns can be shifted in on pri- mary input, tdi and forced onto all digital outputs. tap controller the tap controller is a synchronous finite state machine clocked by the rising edge of primary input, tck. all state transitions are controlled using primary input, tms. the finite state machine is described below.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 206 figure 71. tap controller finite state machine test-logic-reset: the test logic reset state is used to disable the tap logic when the device is in normal mode operation. the state is entered asynchronously by asserting input, trstb. the state is entered synchronously regardless of the current tap con- troller state by forcing input, tms high for 5 tck clock cycles. while in this state, the instruction register is set to the idcode instruction. test-logic-reset run-test-idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir trstb=0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 all transitions dependent on input tms 0 0 0 0 0 1
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 207 run-test-idle: the run test/idle state is used to execute tests. capture-dr: the capture data register state is used to load parallel data into the test data reg- isters selected by the current instruction. if the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. loading occurs on the rising edge of tck. shift-dr: the shift data register state is used to shift the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck. update-dr: the update data register state is used to load a test register's parallel output latch. in general, the output latches are used to control the device. for example, for the extest instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. the parallel output latches are updated on the falling edge of tck. capture-ir: the capture instruction register state is used to load the instruction register with a fixed instruction. the load occurs on the rising edge of tck. shift-ir: the shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck. update-ir: the update instruction register state is used to load a new instruction into the instruction register. the new instruction must be scanned in using the shift-ir state. the load occurs on the falling edge of tck. the pause-dr and pause-ir states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused. the tdo output is enabled during states shift-dr and shift-ir. otherwise, it is tri-stated. boundary scan instructions the following is a description of the standard instructions. each instruction selects an serial test data register path between input, tdi, and output, tdo. bypass the bypass instruction shifts data from input tdi to output tdo with one tck clock period delay. the instruction is used to bypass the device. extest the external test instruction allows testing of the interconnection to other devices. when the current instruction is the extest instruction, the boundary scan regis- ter is place between input tdi and output tdo. primary device inputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 208 the shift-dr state. primary device outputs can be controlled by loading patterns shifted in through input tdi into the boundary scan register using the update-dr state. sample the sample instruction samples all the device inputs and outputs. for this instruc- tion, the boundary scan register is placed between tdi and tdo. primary device inputs and outputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. idcode the identification instruction is used to connect the identification register between tdi and tdo. the device's identification code can then be shifted out using the shift-dr state. stctest the single transport chain instruction is used to test out the tap controller and the boundary scan register during production test. when this instruction is the current instruction, the boundary scan register is connected between tdi and tdo. dur- ing the capture-dr state, the device identification code is loaded into the bound- ary scan register. the code can then be shifted out on output tdo using the shift-dr state. table 47. boundary scan pin order ? pin type output enable -- controls the enable pin of 3 state drivers ? pin type clock -- observable only cell ? pin type input -- observable and controllable input cell ? pin type output3 -- bidirectional 3 state output ? pin type output2 -- three state output order # pin # pin name pin type 1 hiz output enable 2 hiz output enable 3 hiz output enable 4 hiz output enable 5 hiz output enable 6 hiz output enable 7 hiz output enable 8 hiz output enable
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 209 9 e7 scanenbn clock 10 c3 resetn clock 11 e4 abramadd.0 output3 12 e4 abramadd.0 input 13 g5 abramadd.1 output3 14 g5 abramadd.1 input 15 d3 abramadd.2 output3 16 d3 abramadd.2 input 17 f5 abramadd.3 output3 18 f5 abramadd.3 input 19 c2 abramadd.4 output3 20 c2 abramadd.4 input 21 f4 abramadd.5 output3 22 f4 abramadd.5 input 23 e3 abramadd.6 output3 24 e3 abramadd.6 input 25 d2 abramadd.7 output3 26 d2 abramadd.7 input 27 g4 abramadd.8 output3 28 g4 abramadd.8 input 29 f3 abramadd.9 output3 30 f3 abramadd.9 input 31 h5 abramadd.10 output3 32 h5 abramadd.10 input 33 g3 abramadd.11 output3 34 g3 abramadd.11 input 35 e2 abramadd.12 output3 36 e2 abramadd.12 input 37 f2 abramadd.13 output3 38 f2 abramadd.13 input 39 h4 abramadd.14 output3
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 210 40 h4 abramadd.14 input 41 j5 abramadd.15 output3 42 j5 abramadd.15 input 43 g2 abramadd.16 output3 44 g2 abramadd.16 input 45 k4 abramclk output2 46 f1 abramwen output2 47 l5 abramoen output2 48 h3 abramadvn output2 49 j4 abramadspn output2 50 k3 chramclk output2 51 l4 chramadscn output2 52 k5 chramadd17n output2 53 j2 chramoen output2 54 j3 chramwe0n output2 55 l3 chramwe1n output2 56 h2 chramadd.0 output2 57 n5 chramadd.1 output2 58 p5 chramadd.2 output2 59 m5 chramadd.3 output2 60 m3 chramadd.4 output2 61 m4 chramadd.5 output2 62 p4 chramadd.6 output2 63 l2 chramadd.7 output2 64 k2 chramadd.8 output2 65 p3 chramadd.9 output2 66 n4 chramadd.10 output2 67 m2 chramadd.11 output2 68 n3 chramadd.12 output2
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 211 69 n2 chramadd.13 output2 70 n1 chramadd.14 output2 71 r4 chramadd.15 output2 72 r3 chramadd.16 output2 73 r5 chramadd.17 output2 74 p2 chramdata.0 output3 75 p2 chramdata.0 input 76 t5 chramdata.1 output3 77 t5 chramdata.1 input 78 t4 chramdata.2 output3 79 t4 chramdata.2 input 80 t3 chramdata.3 output3 81 t3 chramdata.3 input 82 r2 chramdata.4 output3 83 r2 chramdata.4 input 84 u1 chramdata.5 output3 85 u1 chramdata.5 input 86 t2 chramdata.6 output3 87 t2 chramdata.6 input 88 u2 chramdata.7 output3 89 u2 chramdata.7 input 90 u3 chramdata.8 output3 91 u3 chramdata.8 input 92 v4 chramdata.9 output3 93 v4 chramdata.9 input 94 v2 chramdata.10 output3 95 v2 chramdata.10 input 96 w2 chramdata.11 output3 97 w2 chramdata.11 input 98 u4 chramdata.12 output3 99 u4 chramdata.12 input
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 212 100 v3 chramdata.13 output3 101 v3 chramdata.13 input 102 w4 chramdata.14 output3 103 w4 chramdata.14 input 104 u5 chramdata.15 output3 105 u5 chramdata.15 input 106 w5 chramparity.0 output3 107 w5 chramparity.0 input 108 v5 chramdata.16 output3 109 v5 chramdata.16 input 110 w3 chramdata.17 output3 111 w3 chramdata.17 input 112 aa2 chramdata.18 output3 113 aa2 chramdata.18 input 114 aa3 chramdata.19 output3 115 aa3 chramdata.19 input 116 y2 chramdata.20 output3 117 y2 chramdata.20 input 118 y4 chramdata.21 output3 119 y4 chramdata.21 input 120 aa5 chramdata.22 output3 121 aa5 chramdata.22 input 122 y3 chramdata.23 output3 123 y3 chramdata.23 input 124 y5 chramdata.24 output3 125 y5 chramdata.24 input 126 ab4 chramdata.25 output3 127 ab4 chramdata.25 input 128 ab3 chramdata.26 output3 129 ab3 chramdata.26 input 130 aa4 chramdata.27 output3
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 213 131 aa4 chramdata.27 input 132 ac2 chramdata.28 output3 133 ac2 chramdata.28 input 134 ab2 chramdata.29 output3 135 ab2 chramdata.29 input 136 ac3 chramdata.30 output3 137 ac3 chramdata.30 input 138 ab5 chramdata.31 output3 139 ab5 chramdata.31 input 140 ad3 chramparity.1 output3 141 ad3 chramparity.1 input 142 ad1 alramclk output2 143 ac4 alramadscn output2 144 ad4 alramadd17n output2 145 ad2 alramadd18n output2 146 ae2 alramoen output2 147 af2 alramwe0n output2 148 ae3 alramadd.0 output2 149 ag2 alramadd.1 output2 150 af3 alramadd.2 output2 151 af4 alramadd.3 output2 152 ac5 alramadd.4 output2 153 ae4 alramadd.5 output2 154 ag3 alramadd.6 output2 155 af5 alramadd.7 output2 156 ae6 alramadd.8 output2 157 ae7 alramadd.9 output2 158 ag4 alramadd.10 output2 159 ag5 alramadd.11 output2 160 ah4 alramadd.12 output2 161 af6 alramadd.13 output2
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 214 162 af7 alramadd.14 output2 163 ah5 alramadd.15 output2 164 ag6 alramadd.16 output2 165 ag7 alramadd.17 output2 166 ae8 alramadd.18 output2 167 ah6 alramdata.0 output3 168 ah6 alramdata.0 input 169 ah7 alramdata.1 output3 170 ah7 alramdata.1 input 171 ae9 alramdata.2 output3 172 ae9 alramdata.2 input 173 af8 alramdata.3 output3 174 af8 alramdata.3 input 175 ah8 alramdata.4 output3 176 ah8 alramdata.4 input 177 aj6 alramdata.5 output3 178 aj6 alramdata.5 input 179 af10 alramdata.6 output3 180 af10 alramdata.6 input 181 ag8 alramdata.7 output3 182 ag8 alramdata.7 input 183 af9 alramdata.8 output3 184 af9 alramdata.8 input 185 ae11 alramdata.9 output3 186 ae11 alramdata.9 input 187 ag10 alramdata.10 output3 188 ag10 alramdata.10 input 189 ae10 alramdata.11 output3 190 ae10 alramdata.11 input 191 af11 alramdata.12 output3 192 af11 alramdata.12 input
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 215 193 ah10 alramdata.13 output3 194 ah10 alramdata.13 input 195 ag9 alramdata.14 output3 196 ag9 alramdata.14 input 197 ah9 alramdata.15 output3 198 ah9 alramdata.15 input 199 ag11 alramdata.16 output3 200 ag11 alramdata.16 input 201 ae13 tatmparity output2 202 ae12 tatmsoc output2 203 ae14 tatmwen output2 204 af12 tatmclav.0 clock 205 ag12 tatmclav.1 clock 206 af14 tatmclav.2 clock 207 ah11 tatmclav.3 clock 208 ah12 tatmdata.0 output2 209 af13 tatmdata.1 output2 210 ag14 tatmdata.2 output2 211 ag13 tatmdata.3 output2 212 ah14 tatmdata.4 output2 213 ah13 tatmdata.5 output2 214 aj13 tatmdata.6 output2 215 ag15 tatmdata.7 output2 216 af15 tatmdata.8 output2 217 ae15 tatmdata.9 output2 218 ah15 tatmdata.10 output2 219 ae16 tatmdata.11 output2 220 ag16 tatmdata.12 output2 221 af16 tatmdata.13 output2 222 ah16 tatmdata.14 output2 223 ah17 tatmdata.15 output2
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 216 224 ag18 tatmadd.0 output2 225 aj17 tatmadd.1 output2 226 af18 tatmadd.2 output2 227 ag17 tatmadd.3 output2 228 ah19 tatmadd.4 output2 229 ah18 txdramclk output2 230 af17 txdramba output2 231 af19 txdramcasn output2 232 ag19 txdramrasn output2 233 ae19 txdramwen output2 234 ae17 txdramadd.0 output2 235 ae18 txdramadd.1 output2 236 ah21 txdramadd.2 output2 237 ag20 txdramadd.3 output2 238 ag22 txdramadd.4 output2 239 ah20 txdramadd.5 output2 240 ae21 txdramadd.6 output2 241 af20 txdramadd.7 output2 242 ag21 txdramadd.8 output2 243 af22 txdramcsn.0 output2 244 ah23 txdramcsn.1 output2 245 ae20 txdramdata.0 output3 246 ae20 txdramdata.0 input 247 ah24 txdramdata.1 output3 248 ah24 txdramdata.1 input 249 af21 txdramdata.2 output3 250 af21 txdramdata.2 input 251 ah22 txdramdata.3 output3 252 ah22 txdramdata.3 input 253 ae22 txdramdata.4 output3 254 ae22 txdramdata.4 input
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 217 255 ag23 txdramdata.5 output3 256 ag23 txdramdata.5 input 257 ag24 txdramdata.6 output3 258 ag24 txdramdata.6 input 259 aj24 txdramdata.7 output3 260 aj24 txdramdata.7 input 261 af24 txdramdata.8 output3 262 af24 txdramdata.8 input 263 af23 txdramdata.9 output3 264 af23 txdramdata.9 input 265 ah25 txdramdata.10 output3 266 ah25 txdramdata.10 input 267 ae24 txdramdata.11 output3 268 ae24 txdramdata.11 input 269 ah26 txdramdata.12 output3 270 ah26 txdramdata.12 input 271 ag26 txdramdata.13 output3 272 ag26 txdramdata.13 input 273 ag25 txdramdata.14 output3 274 ag25 txdramdata.14 input 275 ah27 txdramdata.15 output3 276 ah27 txdramdata.15 input 277 af25 txdramdata.16 output3 278 af25 txdramdata.16 input 279 af26 txdramdata.17 output3 280 af26 txdramdata.17 input 281 ae23 txdramdata.18 output3 282 ae23 txdramdata.18 input 283 ag27 txdramdata.19 output3 284 ag27 txdramdata.19 input 285 ae26 txdramdata.20 output3
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 218 286 ae26 txdramdata.20 input 287 ag28 txdramdata.21 output3 288 ag28 txdramdata.21 input 289 ac25 txdramdata.22 output3 290 ac25 txdramdata.22 input 291 af27 txdramdata.23 output3 292 af27 txdramdata.23 input 293 af28 txdramdata.24 output3 294 af28 txdramdata.24 input 295 ae27 txdramdata.25 output3 296 ae27 txdramdata.25 input 297 ad26 txdramdata.26 output3 298 ad26 txdramdata.26 input 299 ac26 txdramdata.27 output3 300 ac26 txdramdata.27 input 301 ad27 txdramdata.28 output3 302 ad27 txdramdata.28 input 303 ae28 txdramdata.29 output3 304 ae28 txdramdata.29 input 305 ac27 txdramdata.30 output3 306 ac27 txdramdata.30 input 307 ab25 txdramdata.31 output3 308 ab25 txdramdata.31 input 309 ad28 sedin0.0 clock 310 ac28 sedin0.1 clock 311 aa25 sedin0.2 clock 312 ab26 sedin0.3 clock 313 ab28 sedin1.0 clock 314 ad29 sedin1.1 clock 315 y26 sedin1.2 clock 316 ab27 sedin1.3 clock
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 219 317 w25 sedin2.0 clock 318 y27 sedin2.1 clock 319 y25 sedin2.2 clock 320 w26 sedin2.3 clock 321 y28 sedin3.0 clock 322 aa27 sedin3.1 clock 323 aa28 sedin3.2 clock 324 w27 sedin3.3 clock 325 u25 sesoci.0 clock 326 v25 sesoci.1 clock 327 t25 sesoci.2 clock 328 v26 sesoci.3 clock 329 w28 rxcellstart clock 330 v28 bpackout.0 output2 331 u26 bpackout.1 output2 332 t27 bpackout.2 output2 333 u27 bpackout.3 output2 334 t28 bpackin.0 clock 335 u28 bpackin.1 clock 336 u29 bpackin.2 clock 337 r27 bpackin.3 clock 338 r26 sdout0.0 output2 339 r25 sdout0.1 output2 340 r28 sdout0.2 output2 341 p25 sdout0.3 output2 342 p27 sdout1.0 output2 343 p26 sdout1.1 output2 344 p28 sdout1.2 output2 345 n28 sdout1.3 output2 346 m27 sdout2.0 output2 347 n29 sdout2.1 output2
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 220 348 m26 sdout2.2 output2 349 n27 sdout2.3 output2 350 l28 sdout3.0 output2 351 m28 sdout3.1 output2 352 n26 sdout3.2 output2 353 l26 sdout3.3 output2 354 l27 ssocout output2 355 l25 dramcke output2 356 n25 rxdramba output2 357 m25 rxdramcasn output2 358 j28 rxdramclk output2 359 k27 rxdramrasn output2 360 h27 rxdramwen output2 361 k28 rxdramadd.0 output2 362 j25 rxdramadd.1 output2 363 k26 rxdramadd.2 output2 364 j27 rxdramadd.3 output2 365 h26 rxdramadd.4 output2 366 g28 rxdramadd.5 output2 367 k25 rxdramadd.6 output2 368 f28 rxdramadd.7 output2 369 j26 rxdramadd.8 output2 370 h28 rxdramcsn.0 output2 371 h25 rxdramcsn.1 output2 372 g27 rxdramdata.0 output3 373 g27 rxdramdata.0 input 374 f27 rxdramdata.1 output3 375 f27 rxdramdata.1 input 376 f29 rxdramdata.2 output3 377 f29 rxdramdata.2 input 378 f26 rxdramdata.3 output3
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 221 379 f26 rxdramdata.3 input 380 g26 rxdramdata.4 output3 381 g26 rxdramdata.4 input 382 e28 rxdramdata.5 output3 383 e28 rxdramdata.5 input 384 f25 rxdramdata.6 output3 385 f25 rxdramdata.6 input 386 d28 rxdramdata.7 output3 387 d28 rxdramdata.7 input 388 d27 rxdramdata.8 output3 389 d27 rxdramdata.8 input 390 e27 rxdramdata.9 output3 391 e27 rxdramdata.9 input 392 c28 rxdramdata.10 output3 393 c28 rxdramdata.10 input 394 e26 rxdramdata.11 output3 395 e26 rxdramdata.11 input 396 b28 rxdramdata.12 output3 397 b28 rxdramdata.12 input 398 g25 rxdramdata.13 output3 399 g25 rxdramdata.13 input 400 c27 rxdramdata.14 output3 401 c27 rxdramdata.14 input 402 d25 rxdramdata.15 output3 403 d25 rxdramdata.15 input 404 e23 rxdramdata.16 output3 405 e23 rxdramdata.16 input 406 c26 rxdramdata.17 output3 407 c26 rxdramdata.17 input 408 e24 rxdramdata.18 output3 409 e24 rxdramdata.18 input
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 222 410 b27 rxdramdata.19 output3 411 b27 rxdramdata.19 input 412 d24 rxdramdata.20 output3 413 d24 rxdramdata.20 input 414 c25 rxdramdata.21 output3 415 c25 rxdramdata.21 input 416 b26 rxdramdata.22 output3 417 b26 rxdramdata.22 input 418 d23 rxdramdata.23 output3 419 d23 rxdramdata.23 input 420 c24 rxdramdata.24 output3 421 c24 rxdramdata.24 input 422 e22 rxdramdata.25 output3 423 e22 rxdramdata.25 input 424 c23 rxdramdata.26 output3 425 c23 rxdramdata.26 input 426 b25 rxdramdata.27 output3 427 b25 rxdramdata.27 input 428 b24 rxdramdata.28 output3 429 b24 rxdramdata.28 input 430 d22 rxdramdata.29 output3 431 d22 rxdramdata.29 input 432 e21 rxdramdata.30 output3 433 e21 rxdramdata.30 input 434 b23 rxdramdata.31 output3 435 b23 rxdramdata.31 input 436 d20 ratmclav.0 clock 437 a24 ratmclav.1 clock 438 e19 ratmclav.2 clock 439 c22 ratmclav.3 clock 440 d21 ratmsoc clock
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 223 441 c20 ratmren output2 442 d19 ratmadd.0 output2 443 e20 ratmadd.1 output2 444 b21 ratmadd.2 output2 445 c21 ratmadd.3 output2 446 c19 ratmadd.4 output2 447 b22 ratmdata.0 clock 448 e17 ratmdata.1 clock 449 e16 ratmdata.2 clock 450 e18 ratmdata.3 clock 451 c18 ratmdata.4 clock 452 d18 ratmdata.5 clock 453 d16 ratmdata.6 input 454 b19 ratmdata.7 clock 455 b20 ratmdata.8 clock 456 c16 ratmdata.9 clock 457 d17 ratmdata.10 clock 458 b18 ratmdata.11 clock 459 c17 ratmdata.12 clock 460 b17 ratmdata.13 clock 461 a17 ratmdata.14 clock 462 d15 ratmdata.15 clock 463 e15 addrdata.0 output3 464 e15 addrdata.0 input 465 b15 addrdata.1 output3 466 b15 addrdata.1 input 467 e14 addrdata.2 output3 468 e14 addrdata.2 input 469 d14 addrdata.3 output3 470 d14 addrdata.3 input 471 c15 addrdata.4 output3
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 224 472 c15 addrdata.4 input 473 b14 addrdata.5 output3 474 b14 addrdata.5 input 475 a13 addrdata.6 output3 476 a13 addrdata.6 input 477 c14 addrdata.7 output3 478 c14 addrdata.7 input 479 b13 addrdata.8 output3 480 b13 addrdata.8 input 481 c13 addrdata.9 output3 482 c13 addrdata.9 input 483 d12 addrdata.10 output3 484 d12 addrdata.10 input 485 b12 addrdata.11 output3 486 b12 addrdata.11 input 487 b11 addrdata.12 output3 488 b11 addrdata.12 input 489 d13 addrdata.13 output3 490 d13 addrdata.13 input 491 c12 addrdata.14 output3 492 c12 addrdata.14 input 493 d11 addrdata.15 output3 494 d11 addrdata.15 input 495 e13 addrdata.16 output3 496 e13 addrdata.16 input 497 e11 addrdata.17 output3 498 e11 addrdata.17 input 499 e12 addrdata.18 output3 500 e12 addrdata.18 input 501 c11 addrdata.19 output3 502 c11 addrdata.19 input
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 225 503 b9 addrdata.20 output3 504 b9 addrdata.20 input 505 c9 addrdata.21 output3 506 c9 addrdata.21 input 507 b10 addrdata.22 output3 508 b10 addrdata.22 input 509 d10 addrdata.23 output3 510 d10 addrdata.23 input 511 e9 addrdata.24 output3 512 e9 addrdata.24 input 513 c10 addrdata.25 output3 514 c10 addrdata.25 input 515 e10 addrdata.26 output3 516 e10 addrdata.26 input 517 d8 addrdata.27 output3 518 d8 addrdata.27 input 519 c8 addrdata.28 output3 520 c8 addrdata.28 input 521 d9 addrdata.29 output3 522 d9 addrdata.29 input 523 b7 addrdata.30 output3 524 b7 addrdata.30 input 525 b8 addrdata.31 output3 526 b8 addrdata.31 input 527 c7 adsn clock 528 e8 write clock 529 a6 csn clock 530 d7 readyn output2 531 b6 intrn output2 532 d6 statstrb output2
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 226 11 application notes 11.1 connecting qrts to qses using gigabit ethernet transceivers qrts can be connected to qses using gigabit ethernet transceivers. several companies, includ- ing amcc and vitesse ? semiconductor corporation, make gigabit ethernet transceivers. vit- esse has three devices: two old (the vsc7135 and the vsc7136) and one new (the vsc7214). the phy layer for gigabit ethernet is taken from fiber channel, so these devices are derived from fiber channel devices. the new vsc7214 is a quad device with integrated 8b/10b encoders. the information about the new vsc7214 is at: http://www.vitesse.com/news/052297.html the existing vsc7135 and vsc7136 devices require an external 8b/10b encoder/decoder. the web site for the existing vsc7135 and vsc7136 (and the vcs7214) is at: http://www.vitesse.com/products/stdprod.html#1 the general interconnection method is to replace the first nibble of four cells with an 8b/10b comma character, copying the present (pres) and multicast (mc) cell bits of all four to the second byte, and not sending the inverted pres bit or the spare (sp) bit. by doing this replacement, a full byte is freed, leaving room for the comma character and allowing a simple interface. the soc signal then needs to be reproduced at the far end. these serialization devices introduce significant latency, which eats into the one-celltime budget for round-trip delay. sending the bp_ack_in(3:0) signal without serialization helps reduce the round-trip latency.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 227 figure 72 shows an example of connecting the qrt to the qse using the vitesse vsc7135 and the vsc7214. another interconnection method is to put all the signals from two or three interfaces over a link, including the soc line. note: the bp_ack_in(3:0) signal does not always go to the same card as the data and soc signals. for example, the data signals might go to the first stage of the fabric and the bp_ack_in(3:0) signal would go to the third stage of the fabric. for this reason, the bp_ack_in(3:0) signal often cannot be combined with the data and soc signals in a serialized interface. these signals can be combined in a switch fabric that had the first and last stages of the fabric on the same card. 11.2 connecting to standard serializer/deserializer chipsets the qrt/qse can be connected using standard serializer/deserializer chipsets such as those pro- vided by hewlett packard ? and national semiconductor ? . the hewlett packard serializer/deserializer chipsets, hdmp-1012/1014, hdmp-1022/1024, and hdmp-1032/1034 (preliminary), are ecl, 5v and 3.3v devices, respectively, that can run at 66 mhz. these devices are ideally suited for gang four applications, where the 16 data lines and a single copy of the soc can be turned into a single differential pair. in certain 3-stage fabrics, the bpack and data can share the serializer: 16 data lines, a single copy of the soc and the four bpack signals can be turned into a single differential pair when the devices run at 62.5 mhz. more infomation about these devices can be found at: http://www.hp.com/hp-comp/fiber/sg/gen_chip.html figure 72. connecting the qrt to gigabit ethernet transceivers qrt (PM73487) pld bp_ack vsc7135 vsc7214 pld qse (pm73488) 16
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 228 the national semiconductor ? serializer/deserializer chipsets, the ds90cr283/284 and the ds90cr285/286, are 5v and 3.3 v devices, respectively, that run at 66 mhz. they use the eia- 644 low voltage differential standard (lvds) to send the signals differentially at a rate of up to 462 mbit/s per lvds data chennel. the setup and hold times match leaving the qrt/qse. com- ing into the qrt/qse, the phase aligners are turned on. these devices are best suited for gang four applications, where the 16 data lines and a single copy of the soc can be accommodated with a single chipset. in certain 3-stage fabrics, the bpack and data can share the serializer: 16 data lines, a single copy of the soc and the four bpack signals. this occurs in situations where the first and last stages are on the same card and the second stage is on another card. the chipset spec requires that skew must be tightly controlled between all the lvds pairs, and all of the outputs must go to the same place. the web site for the devices is: http://www.national.com/pf/ds/ds90cr283.html http://www.national.com/pf/ds/ds90cr284.html http://www.national.com/pf/ds/ds90cr285.html http://www.national.com/pf/ds/ds90cr286.html
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 229 11.3 connecting the qrt to the s/uni-atlas pm7324 the s/uni-atlas pm7324 is a full duplex fault management (fm) oam, performance man- agement (pm) oam, and policing device. it has a utopia interface on the phy side and a sat- urn interface on the other side. it can interface directly to the qrt by utilizing the qrts oc- 12 single phy mode. in the utopia_config register (refer to 7.2.11 utopia_config starting on page 117 ), rx_oc_12c_mode should be set to 1, tx_oc_12c_mode can be set to either 0 or 1, and utopia_2 should be set to 1. please refer to the pmc document pm980583 for a detailed description of this application figure 73 shows an example of connecting the qrt to the s/uni-atlas. 11.4 relationships among various clock domains relationships among various clock domains on the qrt are complex and require careful consid- eration for effective use of the device and optimal performance. duty cycle tolerance for sysclk, atmclk, se_clk and pclk is 60/40. . the maximum operating frequency of the qrt is 100 mhz; however, it is possible to operate the qrt at frequencies below 100 mhz if various relationship constraints are met. frequency rela- tionships also determine the switch speed-up factor and device throughput. phase aligners only converge in a certain frequency range. drams may potentially lose data below a certain operat- ing frequency, and during processor transactions data integrity is guaranteed if the atm_clk-to- sysclk relationship is maintained. figure 73. connecting the qrt to the rcmp-800 receive cell sdram ssram atlas control ssram qrt (PM73487) transmit cell sdram to qse from qse host interface receive utopia level 2 rx_oc_12c_mode = 1 tx_oc_12c_mode = 1 utopia_2 = 1 transmit utopia level 2 pm7324
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 230 11.4.1 relationship among the sysclk, se_clk, and the switch speed-up factor the se_clk relationship with the sysclk is governed by the following equation. se_clk = (66 ? 100) sysclk thus, if sysclk is lowered in frequency, se_clk frequency must be lowered in the same pro- portion to maintain switch fabric speed-up factor at 1.6. switch speed-up factor requirements are switch-topology dependent. for a detailed speed-up fac- tor discussion, refer to the qse (pm73488) long form data sheet . 11.4.2 the phase aligner se_clk frequency constraint phase aligners at the qrt switch fabric interfaces are designed to operate in the se_clk fre- quency range of 50 mhz to 66 mhz. phase aligners are not expected to converge beyond this fre- quency range. if an application requires the se_clk to be less than 50 mhz, it should operate the device with the phase aligners turned off. 11.4.3 the sysclk dram refresh constraint in normal operating mode, the qrt refreshes one row of dram per cell time. a cell time is defined as the sum of 118 se_clk periods. cell time = 118 (1 ? se_clk) a typical sgram requires 1024 rows to be refreshed in 17 ms. a typical sdram requires 2048 rows to be refreshed in 32 ms. this implies a row refresh every 15.6 m s. the se_clk therefore, should never be operated below 7.552 mhz. this also implies that the sysclk never be oper- ated below 11.44 mhz.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 231 11.4.4 relationship between atm_clk and sysclk the maximum frequency allowed at the utopia interface per the utopia level 2 specification is 50 mhz., however, the qrt is designed to operate at up to 55 mhz if the atm layer devices or phy devices permit it. the maximum bandwidth of the qrt is 720 mbit/s when sysclk is at 100 mhz, atm_clk is at 50 mhz, and seclk is at 66 mhz. theoretically, at these clock rates, throughput is a function of sysclk, se_clk, and the switch topology. speeding up the utopia interface can improve the cell transfer delay (ctd), but it cannot improve the throughput. the relationship between the atm_clk and sysclk is defined by the following equation for maximum throughput: atm_clk (52 ? 100) sysclk if atm_clk operates below this ratio, the throughput of the device drops linearly in the same proportion. when atm_clk is operated above this ratio, the qrt utopia interface throttles back, disallowing bandwidth greater than what the device could handle. 11.4.5 relationship between the pclk and the sysclk the upper bound on the pclk is defined by the following equation: pclk (50 ? 100) sysclk if pclk exceeds this bound, the handshake protocol between the processor interface and the rest of the device could be violated. the lower bound on the pclk is defined by the following equation: pclk > (1 ? 8) sysclk if this constraint is not met, incorrect data could be registered during write operations.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 232 appendix a nomenclature a.1 definitions transmit (egress) signals: all signals related to processing the data heading towards the optical/ electrical layer. receive (ingress) signals: all signals related to processing the data heading towards the atm layer. a.2 signal name prefixes many pins have prefixes indicating the function with which they are associated (refer to table 48). a.3 numbers ? hexadecimal numbers are followed by the suffix h , for example: 1 h , 2c h . ? binary numbers are followed by the suffix b , for example: 00 b . ? decimal numbers appear without suffixes. a.4 glossary of abbreviations table 48. prefixes and associated functions pin name prefixes associated functions ratm receive direction of utopia atm ram ram interface rx receive jtag jtag interface tatm transmit direction of utopia atm tx transmit abbreviation description aal atm adaptation layer aal1 atm adaptation layer 1 aal5 atm adaptation layer 5 abr available bit rate ack acknowledgment al address lookup (as in al ram) atm asynchronous transfer mode or atm layer becn backwards explicit congestion notification bp backpressure bpack backpressure acknowledgment
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 233 cam content-addressable memory cas channel associated signaling cbr constant bit rate ccb channel control block cdv cell delay variation ch channel (as in ch ram) clav cell available clp cell loss priority cmos complementary metal oxide semiconductor cpu central processing unit ctd cell transfer delay dqm i/o mask enables dram dynamic random access memory ds0 digital signal level 1 ds1 digital signal level 1 dsi direct status indication efci explicit forward congestion indication eia electronic industries association eof end-of-frame epbga enhanced plastic ball grid array epd early packet discard er explicit rate fecn forward explicit congestion notification fifo first in, first out fm fault management gfc generic flow control gp general purpose hec header error check irt input half of qrt lan local area network lsb least significant bit lsw least significant word lv low voltage differential lvds low voltage differential standard mb mark bit abbreviation description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 234 mbs maximum burst size mc multicast mcr minimum cell rate mctg multicast translation group mnack medium negative acknowledgment or mid-switch negative acknowledgment mod modulo mphy multi-phy msb most significant bit msp multiplexed status polling msw most significant word nack negative acknowledgment nrtvbr non real-time variable bit rate oam operations, administration, and maintenance oc-3 optical carrier level 3 (155.52 mbit/s) oc-12 optical carrier level 12 (622.08 mbit/s) onack output negative acknowledgment ort output half of qrt pb proportional bandwidth phy physical or physical layer or physical layer device pld programmable logic device pm performance management ppd partial packet discard ptd packet tail discard pti payload type indicator qos quality-of-service qrt PM73487 qse pm73488 ram random access memory rcmp-800 routing control, monitoring and policing for 800 mbit/s (pmc-sierra device) rsf receive switch fabric rtvbr real-time variable bit rate rx receive sar segmentation and reassembly saturn sonet/atm user network (refers to the interface defined by the saturn devel- opment group) abbreviation description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 235 sc service class scr sustainable cell rate scq service class queue sdram synchronous dynamic random access memory sesar switched ethernet segmentation and reassembly sgram synchronous graphic random access memory sn sequence number soj small outline j-lead soc start-of-cell sp spare sram static random access memory ssram synchronous static random access memory tbit/s terabits per second tsf transmit switch fabric ttl transistor-totransitor logic tx transmit ubr unspecified bit rate uni user-to-network interface upc usage parameter control utopia universal test and operations interface for atm vbr variable bit rate vc virtual channel vcc virtual channel connection vci virtual channel identifier vi virtual input vih input high voltage vil input low voltage vo virtual output vp virtual path vpc virtual path connection vpi virtual path identifier uni user-to-network interface vbr variable bit rate wan wide area network abbreviation description
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 236 appendix b references ?atm forum, atm user-network interface specification , v3.0, september 10, 1993. ?atm forum, utopia C an atm phy data path interface, level 1 , v2.01, february, 1994. ?atm forum, utopia C an atm - phy interface specification , level 2 , v1.0, june 1995. ? ieee 1149.1, standard test access port and boundary scan architecture , may 21, 1990. ? itu (ccitt) recommendation i.432, b-isdn user-network interface - physical interface specification , june 1990. ? pmc-sierra, inc., atm switch fabric element (qse C pm73488) long form data sheet .
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 237 appendix c ram selection table 49. qrt ram selection name description type size suggested rams interface notes ab_ram contains head & tail pointers and sent/drop counters for rx queues ssram 128kx18 mt58lc 128k18 d9-10 mt58lc 128k18 c6-10 17bit multiplex bus. see note b al_ram vpi/vci address lookup tables. cell buffer pointers, service order tables and multicast pointer fifos. (different alram_config modes correspond to different vpi/vci ranges and cell buffer sizes) ssram 128kx18 256kx18 * 512kx18 * (see section 7.2.4 of the PM73487 data sheet ) 1. alram_config mode 0 = 64kx18 2. alram_config mode 1 = 128kx 18 3. alram_config mode 2 = 256kx18 4. alram_config mode 3 = 512kx18 mt58lc 128k18 d9-10 mt58lc 128k18 c6-10 mt58lc 256k18 d9-10 mt58lc 256k18 c6-10 17bit data, 18bit address see note b can use 2 256kx18 scd chips by setting alram_type = 1 (see datasheet section 7.2.4) ch_ram per tx/rx channel table info. ssram 64kx36 = 4k vcs 128kx36 = 8k vcs * 256kx36 = 16k vcs * mt58lc 128k18 c6-10 mt58lc 256k18 c6-10 34bit data, 17bit address see note b rx dram receive cell buffers. per vc queuing. 64k cell buffers. sdram or sgram 1mx16 sdram * 256kx32 sgram mt48lc 1m16 a1-10 (sdram) mt41lc 256k32 d5-10 (sgram) 32 bit data, 9bit address, 2bit cs. sdram, must use 2 chips (64k cells). sgram, can use 1 or 2 chips (16k or 32k cells). tx dram transmit cell buffers. per virtual output & service class queuing. 64k cell buffers. sdram or sgram 1mx16 sdram * 256kx32 sgram mt48lc 1m16 a1-10 (sdram) mt41lc 256k32 d5-10 (sgram) 32 bit data, 9bit address, 2bit cs. sdram, must use 2 chips (64k cells). sgram, can use 1 or 2 chips (16k or 32k cells). * most common memory configurations. note b : scd ssram can be used if the entire address space of the ram bank is within 1 ram chip. scd = single cycle deselect memory. the notation d9 can be seen in the name of these ssram. dcd = double c y cle deselect memor y . the notation c6 can be seen in the name of these ssram.
PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet 238 ordering information table 50 lists the ordering information. table 50. ordering information part number description PM73487-pi 503-pin enhanced plastic ball grid array (epbga) package
PM73487 qrt PM73487 qrt pmc-sierra, inc. pmc-980618 issue 3 622 mbps atm traffic management device released datasheet none of the information contained in this document constitutes an express or implied warranty by pmc-sierra, inc. as to the suf ficiency, fitness, or suitability for a particular purpose of any such information of the fitness or suitability for a particular purpose, merchantab ility, performance, compatibility with other parts or systems, of any of the products of pmc-sierra, inc., or any portion thereof, referred to in this document. pmc-sierra, inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not l imited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use or reliance upon the information, whether or not pmc-sierra, inc. has been ad vised of the possibility of such damage. ? 1999 pmc-sierra, inc. pmc-980618 (r3) ref pmc-981001(r2) issue date: june 1999 contacting pmc-sierra, inc. pmc-sierra, inc. 105-8555 baxter place burnaby b.c. canada v5a 4v7 tel: (604) 415-6000 fax: (604) 415-6200 document information: document@pmc-sierra.com corporate information: info@pmc-sierra.com application information: apps@pmc-sierra.com (604) 415-4533 web site: http://www.pmc-sierra.com

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